| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <07f09c8a-c797-4142-a339-6c0bdff466e7@quicinc.com>
Date: Thu, 9 Jan 2025 17:47:38 +0800
From: Yongxing Mou <quic_yongmou@...cinc.com>
To: Bjorn Andersson <andersson@...nel.org>
CC: Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, <linux-arm-msm@...r.kernel.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
Ritesh Kumar <quic_riteshk@...cinc.com>
Subject: Re: [PATCH 1/2] arm64: dts: qcom: qcs8300: add DisplayPort device
nodes
On 2025/1/9 7:06, Bjorn Andersson wrote:
> On Wed, Nov 27, 2024 at 06:45:13PM +0800, Yongxing Mou wrote:
>> Add device tree nodes for the DPTX0 controller with their
>> corresponding PHYs found on Qualcomm QCS8300 SoC.
>>
>> Signed-off-by: Yongxing Mou <quic_yongmou@...cinc.com>
>
> Please rebase, test and resubmit this together, in the same series, with
> the mdss patch.
>
> Regards,
> Bjorn
>
sure. got it. I will integrate the mdss dts change with this and submit
it together.thanks.
>> ---
>> arch/arm64/boot/dts/qcom/qcs8300.dtsi | 115 +++++++++++++++++++++++++++++++++-
>> 1 file changed, 114 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>> index 1642e2863affd5af0b4f68118a47b7a74b76df95..28deba0a389641b4dddbf4505d6f44c6607aa03b 100644
>> --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>> @@ -987,6 +987,19 @@ mdss_mdp: display-controller@...1000 {
>> interrupt-parent = <&mdss>;
>> interrupts = <0>;
>>
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@0 {
>> + reg = <0>;
>> +
>> + dpu_intf0_out: endpoint {
>> + remote-endpoint = <&mdss_dp0_in>;
>> + };
>> + };
>> + };
>> +
>> mdp_opp_table: opp-table {
>> compatible = "operating-points-v2";
>>
>> @@ -1011,6 +1024,104 @@ opp-650000000 {
>> };
>> };
>> };
>> +
>> + mdss_dp0_phy: phy@...2a00 {
>> + compatible = "qcom,qcs8300-edp-phy";
>> +
>> + reg = <0x0 0x0aec2a00 0x0 0x200>,
>> + <0x0 0x0aec2200 0x0 0xd0>,
>> + <0x0 0x0aec2600 0x0 0xd0>,
>> + <0x0 0x0aec2000 0x0 0x1c8>;
>> +
>> + clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
>> + <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>;
>> + clock-names = "aux",
>> + "cfg_ahb";
>> +
>> + #clock-cells = <1>;
>> + #phy-cells = <0>;
>> +
>> + status = "disabled";
>> + };
>> +
>> + mdss_dp0: displayport-controller@...4000 {
>> + compatible = "qcom,qcs8300-dp";
>> +
>> + reg = <0x0 0x0af54000 0x0 0x104>,
>> + <0x0 0x0af54200 0x0 0x0c0>,
>> + <0x0 0x0af55000 0x0 0x770>,
>> + <0x0 0x0af56000 0x0 0x09c>;
>> +
>> + interrupt-parent = <&mdss>;
>> + interrupts = <12>;
>> +
>> + clocks = <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>,
>> + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
>> + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>,
>> + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
>> + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
>> + clock-names = "core_iface",
>> + "core_aux",
>> + "ctrl_link",
>> + "ctrl_link_iface",
>> + "stream_pixel";
>> + assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
>> + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
>> + assigned-clock-parents = <&mdss_dp0_phy 0>,
>> + <&mdss_dp0_phy 1>;
>> + phys = <&mdss_dp0_phy>;
>> + phy-names = "dp";
>> +
>> + operating-points-v2 = <&dp_opp_table>;
>> + power-domains = <&rpmhpd RPMHPD_MMCX>;
>> +
>> + #sound-dai-cells = <0>;
>> +
>> + status = "disabled";
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@0 {
>> + reg = <0>;
>> +
>> + mdss_dp0_in: endpoint {
>> + remote-endpoint = <&dpu_intf0_out>;
>> + };
>> + };
>> +
>> + port@1 {
>> + reg = <1>;
>> +
>> + mdss_dp0_out: endpoint { };
>> + };
>> + };
>> +
>> + dp_opp_table: opp-table {
>> + compatible = "operating-points-v2";
>> +
>> + opp-160000000 {
>> + opp-hz = /bits/ 64 <160000000>;
>> + required-opps = <&rpmhpd_opp_low_svs>;
>> + };
>> +
>> + opp-270000000 {
>> + opp-hz = /bits/ 64 <270000000>;
>> + required-opps = <&rpmhpd_opp_svs>;
>> + };
>> +
>> + opp-540000000 {
>> + opp-hz = /bits/ 64 <540000000>;
>> + required-opps = <&rpmhpd_opp_svs_l1>;
>> + };
>> +
>> + opp-810000000 {
>> + opp-hz = /bits/ 64 <810000000>;
>> + required-opps = <&rpmhpd_opp_nom>;
>> + };
>> + };
>> + };
>> };
>>
>> dispcc: clock-controller@...0000 {
>> @@ -1020,7 +1131,9 @@ dispcc: clock-controller@...0000 {
>> <&rpmhcc RPMH_CXO_CLK>,
>> <&rpmhcc RPMH_CXO_CLK_A>,
>> <&sleep_clk>,
>> - <0>, <0>, <0>, <0>,
>> + <&mdss_dp0_phy 0>,
>> + <&mdss_dp0_phy 1>,
>> + <0>, <0>,
>> <0>, <0>, <0>, <0>;
>> power-domains = <&rpmhpd RPMHPD_MMCX>;
>> #clock-cells = <1>;
>>
>> --
>> 2.34.1
>>
Powered by blists - more mailing lists