linux-kernel - [PATCH V3] phy: freescale: fsl-samsung-hdmi: fix build error in fsl_samsung_hdmi_phy_configure_pll_lock

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Message-Id: <5b9a5f765f075263498f9a7b62b0b1030d87b6ba.1736476210.git.xiaopei01@kylinos.cn>
Date: Fri, 10 Jan 2025 10:32:47 +0800
From: Pei Xiao <xiaopei01@...inos.cn>
To: vkoul@...nel.org,
	aford173@...il.com,
	linux-phy@...ts.infradead.org,
	linux-kernel@...r.kernel.org
Cc: Pei Xiao <xiaopei01@...inos.cn>
Subject: [PATCH V3] phy: freescale: fsl-samsung-hdmi: fix build error in fsl_samsung_hdmi_phy_configure_pll_lock_det

FIELD_PREP() checks that a value fits into the available bitfield,
but the index div equals to 4,is out of range.

which gcc complains about:
In function ‘fsl_samsung_hdmi_phy_configure_pll_lock_det’,
inlined from ‘fsl_samsung_hdmi_phy_configure’ at
drivers/phy/freescale/phy-fsl-samsung-hdmi.c :470:2:
././include/linux/compiler_types.h:542:38: error: call to ‘__compiletime_assert_538’
declared with attribute error: FIELD_PREP: value too large for the field
  542 |  _compiletime_assert(condition, msg, __compiletime_assert_,
__COUNTER__)
      |                                      ^
././include/linux/compiler_types.h:523:4: note: in definition of
macro ‘__compiletime_assert’ 523 |    prefix ## suffix();
      |    ^~~~~~
././include/linux/compiler_types.h:542:2: note: in expansion of macro
‘_compiletime_assert’
  542 |  _compiletime_assert(condition, msg, __compiletime_assert_,
 __COUNTER__)

REG12_CK_DIV_MASK only two bit, limit div to range 0~3,
so build error will fix.

Fixes: d567679f2b6a ("phy: freescale: fsl-samsung-hdmi: Clean up fld_tg_code calculation")
Signed-off-by: Pei Xiao <xiaopei01@...inos.cn>
---
V3: change to use do-while
V2: change to use logical AND
---
 drivers/phy/freescale/phy-fsl-samsung-hdmi.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c
index 5eac70a1e858..aa233ca25a4d 100644
--- a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c
+++ b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c
@@ -332,14 +332,15 @@ fsl_samsung_hdmi_phy_configure_pll_lock_det(struct fsl_samsung_hdmi_phy *phy,
 	u32 pclk = cfg->pixclk;
 	u32 fld_tg_code;
 	u32 int_pllclk;
-	u8 div;
+	u8 div = 0;
 
 	/* Find int_pllclk speed */
-	for (div = 0; div < 4; div++) {
+	do {
 		int_pllclk = pclk / (1 << div);
-		if (int_pllclk < (50 * MHZ))
+		if (int_pllclk < (50 * MHZ) || div >= 3)
 			break;
-	}
+		div++;
+	} while (1);
 
 	writeb(FIELD_PREP(REG12_CK_DIV_MASK, div), phy->regs + PHY_REG(12));
 
-- 
2.25.1