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Message-Id: <20250110-wip-bl-ad3552r-axi-v0-iio-testing-carlos-v3-9-ab42aef0d840@baylibre.com>
Date: Fri, 10 Jan 2025 11:24:21 +0100
From: Angelo Dureghello <adureghello@...libre.com>
To: Lars-Peter Clausen <lars@...afoo.de>,
Michael Hennerich <Michael.Hennerich@...log.com>,
Jonathan Cameron <jic23@...nel.org>, David Lechner <dlechner@...libre.com>,
Nuno Sa <nuno.sa@...log.com>
Cc: Jonathan Cameron <Jonathan.Cameron@...wei.com>,
linux-iio@...r.kernel.org, linux-kernel@...r.kernel.org,
Angelo Dureghello <adureghello@...libre.com>
Subject: [PATCH v3 9/9] iio: dac: ad3552r-hs: update function name (non
functional)
From: Angelo Dureghello <adureghello@...libre.com>
Update ad3552r_qspi_update_reg_bits function name to a more
generic name, since used mode can be SIMPLE/DUAL/QUAD SPI.
Signed-off-by: Angelo Dureghello <adureghello@...libre.com>
---
drivers/iio/dac/ad3552r-hs.c | 64 ++++++++++++++++++++------------------------
1 file changed, 29 insertions(+), 35 deletions(-)
diff --git a/drivers/iio/dac/ad3552r-hs.c b/drivers/iio/dac/ad3552r-hs.c
index 4600a9e84dfc..7f3a70cfbef8 100644
--- a/drivers/iio/dac/ad3552r-hs.c
+++ b/drivers/iio/dac/ad3552r-hs.c
@@ -56,9 +56,9 @@ struct ad3552r_hs_state {
u32 config_d;
};
-static int ad3552r_qspi_update_reg_bits(struct ad3552r_hs_state *st,
- u32 reg, u32 mask, u32 val,
- size_t xfer_size)
+static int ad3552r_update_reg_bits(struct ad3552r_hs_state *st,
+ u32 reg, u32 mask, u32 val,
+ size_t xfer_size)
{
u32 rval;
int ret;
@@ -206,9 +206,8 @@ static int ad3552r_hs_buffer_postenable(struct iio_dev *indio_dev)
*/
/* Primary region access, set streaming mode (now in SPI + SDR). */
- ret = ad3552r_qspi_update_reg_bits(st,
- AD3552R_REG_ADDR_INTERFACE_CONFIG_B,
- AD3552R_MASK_SINGLE_INST, 0, 1);
+ ret = ad3552r_update_reg_bits(st, AD3552R_REG_ADDR_INTERFACE_CONFIG_B,
+ AD3552R_MASK_SINGLE_INST, 0, 1);
if (ret)
return ret;
@@ -217,10 +216,9 @@ static int ad3552r_hs_buffer_postenable(struct iio_dev *indio_dev)
* len value so it's not cleared hereafter when enabling streaming mode
* (cleared by CS_ up).
*/
- ret = ad3552r_qspi_update_reg_bits(st,
- AD3552R_REG_ADDR_TRANSFER_REGISTER,
- AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE,
- AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE, 1);
+ ret = ad3552r_update_reg_bits(st, AD3552R_REG_ADDR_TRANSFER_REGISTER,
+ AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE,
+ AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE, 1);
if (ret)
goto exit_err_streaming;
@@ -250,7 +248,7 @@ static int ad3552r_hs_buffer_postenable(struct iio_dev *indio_dev)
/*
* From here onward mode is DDR, so reading any register is not possible
- * anymore, including calling "ad3552r_qspi_update_reg_bits" function.
+ * anymore, including calling "ad3552r_update_reg_bits" function.
*/
/* Set target to best high speed mode (D or QSPI). */
@@ -351,18 +349,16 @@ static int ad3552r_hs_buffer_predisable(struct iio_dev *indio_dev)
* Back to simple SPI for secondary region too now, so to be able to
* dump/read registers there too if needed.
*/
- ret = ad3552r_qspi_update_reg_bits(st,
- AD3552R_REG_ADDR_TRANSFER_REGISTER,
- AD3552R_MASK_MULTI_IO_MODE,
- AD3552R_SPI, 1);
+ ret = ad3552r_update_reg_bits(st, AD3552R_REG_ADDR_TRANSFER_REGISTER,
+ AD3552R_MASK_MULTI_IO_MODE,
+ AD3552R_SPI, 1);
if (ret)
return ret;
/* Back to single instruction mode, disabling loop. */
- ret = ad3552r_qspi_update_reg_bits(st,
- AD3552R_REG_ADDR_INTERFACE_CONFIG_B,
- AD3552R_MASK_SINGLE_INST,
- AD3552R_MASK_SINGLE_INST, 1);
+ ret = ad3552r_update_reg_bits(st, AD3552R_REG_ADDR_INTERFACE_CONFIG_B,
+ AD3552R_MASK_SINGLE_INST,
+ AD3552R_MASK_SINGLE_INST, 1);
if (ret)
return ret;
@@ -379,10 +375,10 @@ static inline int ad3552r_hs_set_output_range(struct ad3552r_hs_state *st,
else
val = FIELD_PREP(AD3552R_MASK_CH1_RANGE, mode);
- return ad3552r_qspi_update_reg_bits(st,
- AD3552R_REG_ADDR_CH0_CH1_OUTPUT_RANGE,
- AD3552R_MASK_CH_OUTPUT_RANGE_SEL(ch),
- val, 1);
+ return ad3552r_update_reg_bits(st,
+ AD3552R_REG_ADDR_CH0_CH1_OUTPUT_RANGE,
+ AD3552R_MASK_CH_OUTPUT_RANGE_SEL(ch),
+ val, 1);
}
static int ad3552r_hs_reset(struct ad3552r_hs_state *st)
@@ -398,10 +394,10 @@ static int ad3552r_hs_reset(struct ad3552r_hs_state *st)
fsleep(10);
gpiod_set_value_cansleep(st->reset_gpio, 0);
} else {
- ret = ad3552r_qspi_update_reg_bits(st,
- AD3552R_REG_ADDR_INTERFACE_CONFIG_A,
- AD3552R_MASK_SOFTWARE_RESET,
- AD3552R_MASK_SOFTWARE_RESET, 1);
+ ret = ad3552r_update_reg_bits(st,
+ AD3552R_REG_ADDR_INTERFACE_CONFIG_A,
+ AD3552R_MASK_SOFTWARE_RESET,
+ AD3552R_MASK_SOFTWARE_RESET, 1);
if (ret)
return ret;
}
@@ -534,19 +530,17 @@ static int ad3552r_hs_setup(struct ad3552r_hs_state *st)
val = ret;
- ret = ad3552r_qspi_update_reg_bits(st,
- AD3552R_REG_ADDR_SH_REFERENCE_CONFIG,
- AD3552R_MASK_REFERENCE_VOLTAGE_SEL,
- val, 1);
+ ret = ad3552r_update_reg_bits(st, AD3552R_REG_ADDR_SH_REFERENCE_CONFIG,
+ AD3552R_MASK_REFERENCE_VOLTAGE_SEL,
+ val, 1);
if (ret)
return ret;
ret = ad3552r_get_drive_strength(st->dev, &val);
if (!ret) {
- ret = ad3552r_qspi_update_reg_bits(st,
- AD3552R_REG_ADDR_INTERFACE_CONFIG_D,
- AD3552R_MASK_SDO_DRIVE_STRENGTH,
- val, 1);
+ ret = ad3552r_update_reg_bits(st,
+ AD3552R_REG_ADDR_INTERFACE_CONFIG_D,
+ AD3552R_MASK_SDO_DRIVE_STRENGTH, val, 1);
if (ret)
return ret;
}
--
2.47.0
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