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Message-ID:
<VI1PR09MB2333E8B63445C266F455B55E941E2@VI1PR09MB2333.eurprd09.prod.outlook.com>
Date: Sun, 12 Jan 2025 07:47:23 +0000
From: Vladimir Kondratiev <Vladimir.Kondratiev@...ileye.com>
To: Rob Herring <robh@...nel.org>
CC: Anup Patel <anup@...infault.org>, Thomas Gleixner <tglx@...utronix.de>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
Paul Walmsley <paul.walmsley@...ive.com>, Palmer Dabbelt
<palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>,
"linux-riscv@...ts.infradead.org" <linux-riscv@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>
Subject: Re: [PATCH v4 1/2] dt-bindings: interrupt-controller: add
risc-v,aplic hart indexes
>Wouldn't using the 'cpus' property linking to each cpu/hart node work?
>Rob
Hi,
unfortunately, per-CPU property would not work. "hart index" defined per
interrupt domain, and different controllers may define it differently.
This is from the "4.3 Hart index numbers" section of the interrupts spec found at
https://github.com/riscv/riscv-aia
Within a given interrupt domain, each of the domain’s harts has a unique index
number in the range 0 to 2^14 − 1 (= 16,383).
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