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Message-Id: <20250113150933.65121-1-luxu.kernel@bytedance.com> Date: Mon, 13 Jan 2025 23:09:28 +0800 From: Xu Lu <luxu.kernel@...edance.com> To: daniel.lezcano@...aro.org, tglx@...utronix.de, anup@...infault.org, paul.walmsley@...ive.com, palmer@...belt.com Cc: lihangjing@...edance.com, xieyongji@...edance.com, linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org, Xu Lu <luxu.kernel@...edance.com> Subject: [PATCH 0/5] riscv: irqchip: Optimization of interrupt handling This patch series provides some optimization for the existing interrupt handling procedure. First, it tries to make a balance between interrupt priority and fairness to avoid interrupts with lower priority get starved. Also, it inserts barriers to ensure the order between normal memory writes and IPI issuing. Xu Lu (5): irqchip/riscv-intc: Balance priority and fairness during irq handling irqchip/riscv-imsic: Add a threshold to ext irq handling times irqchip/riscv-imsic: Use wmb() to order normal writes and IPI writes irqchip/timer-clint: Use wmb() to order normal writes and IPI writes irqchip/aclint-sswi: Use wmb() to order normal writes and IPI writes drivers/clocksource/timer-clint.c | 6 ++++ drivers/irqchip/irq-riscv-imsic-early.c | 37 +++++++++++++------- drivers/irqchip/irq-riscv-intc.c | 32 +++++++++++++---- drivers/irqchip/irq-thead-c900-aclint-sswi.c | 6 ++++ 4 files changed, 62 insertions(+), 19 deletions(-) -- 2.20.1
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