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Message-ID: <20250113164728.00005f40@huawei.com>
Date: Mon, 13 Jan 2025 16:47:28 +0000
From: Jonathan Cameron <Jonathan.Cameron@...wei.com>
To: Gregory Price <gourry@...rry.net>
CC: Robert Richter <rrichter@....com>, Alison Schofield
	<alison.schofield@...el.com>, Vishal Verma <vishal.l.verma@...el.com>, "Ira
 Weiny" <ira.weiny@...el.com>, Dan Williams <dan.j.williams@...el.com>, "Dave
 Jiang" <dave.jiang@...el.com>, Davidlohr Bueso <dave@...olabs.net>,
	<linux-cxl@...r.kernel.org>, <linux-kernel@...r.kernel.org>, "Fabio M. De
 Francesco" <fabio.m.de.francesco@...ux.intel.com>, Terry Bowman
	<terry.bowman@....com>
Subject: Re: [PATCH v1 04/29] cxl/pci: Add comments to cxl_hdm_decode_init()

On Tue, 7 Jan 2025 11:51:23 -0500
Gregory Price <gourry@...rry.net> wrote:

> On Tue, Jan 07, 2025 at 03:09:50PM +0100, Robert Richter wrote:
> > There are various configuration cases of HDM decoder registers causing
> > different code paths. Add comments to cxl_hdm_decode_init() to better
> > explain them.
> > 
> > Signed-off-by: Robert Richter <rrichter@....com>
> > ---
> >  drivers/cxl/core/pci.c | 11 ++++++++++-
> >  1 file changed, 10 insertions(+), 1 deletion(-)
> >   
> 
> This addresses some of my prior questions, but I still think this
> function is worth some extra scrutiny.
> 
> Reviewed-by: Gregory Price <gourry@...rry.net>
Definitely an improvement.

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@...wei.com>

> 
> > diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
> > index c7050c13f71a..4d2154457efb 100644
> > --- a/drivers/cxl/core/pci.c
> > +++ b/drivers/cxl/core/pci.c
> > @@ -416,9 +416,17 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm,
> >  	if (global_ctrl & CXL_HDM_DECODER_ENABLE || (!hdm && info->mem_enabled))
> >  		return devm_cxl_enable_mem(&port->dev, cxlds);
> >  
> > +	/*
> > +	 * If the HDM Decoder Capability does not exist and DVSEC was
> > +	 * not setup, the DVSEC based emulation cannot be used.
> > +	 */
> >  	if (!hdm)
> >  		return -ENODEV;
> >  
> > +	/*
> > +	 * The HDM Decoder Capability exists but is globally disabled.
> > +	 */
> > +
> >  	/*
> >  	 * Per CXL 2.0 Section 8.1.3.8.3 and 8.1.3.8.4 DVSEC CXL Range 1 Base
> >  	 * [High,Low] when HDM operation is enabled the range register values
> > @@ -426,7 +434,8 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm,
> >  	 * DVSEC Range 1,2 to HDM Decoder Range 0,1. So, non-zero info->ranges
> >  	 * are expected even though Linux does not require or maintain that
> >  	 * match. If at least one DVSEC range is enabled and allowed, skip HDM
> > -	 * Decoder Capability Enable.
> > +	 * Decoder Capability Enable. Else, use the HDM Decoder Capability and
> > +	 * enable it.
> >  	 */
> >  	if (!info->mem_enabled) {
> >  		rc = devm_cxl_enable_hdm(&port->dev, cxlhdm);
> > -- 
> > 2.39.5
> >   


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