lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <bc4f90fb76f82b54069b229291461d5e86a21090.camel@surriel.com>
Date: Mon, 13 Jan 2025 16:08:45 -0500
From: Rik van Riel <riel@...riel.com>
To: Jann Horn <jannh@...gle.com>, thomas.lendacky@....com
Cc: x86@...nel.org, linux-kernel@...r.kernel.org, bp@...en8.de, 
	peterz@...radead.org, dave.hansen@...ux.intel.com,
 zhengqi.arch@...edance.com, 	nadav.amit@...il.com, kernel-team@...a.com,
 linux-mm@...ck.org, 	akpm@...ux-foundation.org
Subject: Re: [PATCH v4 04/12] x86/mm: get INVLPGB count max from CPUID

On Mon, 2025-01-13 at 16:50 +0100, Jann Horn wrote:
> On Sun, Jan 12, 2025 at 4:55 PM Rik van Riel <riel@...riel.com>
> wrote:
> > +       /* Max number of pages INVLPGB can invalidate in one shot
> > */
> > +       if (boot_cpu_has(X86_FEATURE_INVLPGB)) {
> > +               cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
> > +               invlpgb_count_max = (edx & 0xffff) + 1;
> 
> I assume the +1 is just a weird undocumented (or weirdly documented)
> encoding?
> https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/24594.pdf
> says that field InvlpgbCountMax contains the "Maximum page count for
> INVLPGB instruction" and doesn't mention having to add 1 from what I
> can tell.
> 
The way I read the documentation, the number
passed in to invlpgb (and retrieved from cpuid)
corresponds to the number of extra pages
invalidated beyond the first page at the specified
address.

Things have not exploded on me invalidating
multiple pages at once in larger ranges, so I 
suspect my reading is right, but it would be
nice for one of the AMD people to confirm :)

-- 
All Rights Reversed.

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ