linux-kernel - Re: [PATCH RFC 08/11] drm/msm/dsi: Add support for SM8750

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Message-ID: <uyidfuh5ul5kcg4keeev6yagmjc5ksun626dyb6kdgwegc76d7@iu7ggdhgt5qr>
Date: Mon, 13 Jan 2025 10:29:54 +0200
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Cc: Rob Clark <robdclark@...il.com>, 
	Abhinav Kumar <quic_abhinavk@...cinc.com>, Sean Paul <sean@...rly.run>, 
	Marijn Suijten <marijn.suijten@...ainline.org>, David Airlie <airlied@...il.com>, 
	Simona Vetter <simona@...ll.ch>, Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>, 
	Maxime Ripard <mripard@...nel.org>, Thomas Zimmermann <tzimmermann@...e.de>, 
	Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, 
	Conor Dooley <conor+dt@...nel.org>, Krishna Manikandan <quic_mkrishn@...cinc.com>, 
	Jonathan Marek <jonathan@...ek.ca>, Kuogee Hsieh <quic_khsieh@...cinc.com>, 
	Neil Armstrong <neil.armstrong@...aro.org>, linux-arm-msm@...r.kernel.org, dri-devel@...ts.freedesktop.org, 
	freedreno@...ts.freedesktop.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, 
	Srini Kandagatla <srinivas.kandagatla@...aro.org>
Subject: Re: [PATCH RFC 08/11] drm/msm/dsi: Add support for SM8750

On Fri, Jan 10, 2025 at 01:43:28PM +0100, Krzysztof Kozlowski wrote:
> On 10/01/2025 10:17, Dmitry Baryshkov wrote:
> > On Fri, Jan 10, 2025 at 09:59:26AM +0100, Krzysztof Kozlowski wrote:
> >> On 10/01/2025 00:18, Dmitry Baryshkov wrote:
> >>> On Thu, Jan 09, 2025 at 02:08:35PM +0100, Krzysztof Kozlowski wrote:
> >>>> Add support for DSI PHY v7.0 on Qualcomm SM8750 SoC which comes with two
> >>>> differences worth noting:
> >>>>
> >>>> 1. ICODE_ACCUM_STATUS_LOW and ALOG_OBSV_BUS_STATUS_1 registers - their
> >>>>    offsets were just switched.  Currently these registers are not used
> >>>>    in the driver, so the easiest is to document both but keep them
> >>>>    commented out to avoid conflict.
> >>>>
> >>>> 2. DSI PHY PLLs, the parents of pixel and byte clocks, cannot be used as
> >>>>    parents before they are prepared and initial rate is set.  Therefore
> >>>>    assigned-clock-parents are not working here and driver is responsible
> >>>>    for reparenting clocks with proper procedure: see dsi_clk_init_6g_v2_9().
> >>>
> >>> Isn't it a description of CLK_SET_PARENT_GATE and/or
> >>
> >> No - must be gated accross reparent - so opposite.
> >>
> >>> CLK_OPS_PARENT_ENABLE ?
> >>
> >> Yes, but does not work. Probably enabling parent, before
> >> assigned-clocks-parents, happens still too early:
> >>
> >> [    1.623554] DSI PLL(0) lock failed, status=0x00000000
> >> [    1.623556] PLL(0) lock failed
> >> [    1.624650] ------------[ cut here ]------------
> >> [    1.624651] disp_cc_mdss_byte0_clk_src: rcg didn't update its
> >> configuration.
> >>
> >> Or maybe something is missing in the DSI PHY PLL driver?
> > 
> > Do you have the no-zero-freq workaround?
> 
> Yes, it is necessary also for my variant. I did not include it here, but
> I should mention it in the cover letter.

Could you please possibly backtrace the corresponding enable() calls?
I'd let Stephen and/or Bjorn or Konrad to correct me, but I think that
such requirement should be handled by the framework instead of having
the drivers to manually reparent the clocks.

-- 
With best wishes
Dmitry