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Message-ID: <d247d5967e3920a2a65499bbfa01d2442dd2e958.camel@surriel.com>
Date: Tue, 14 Jan 2025 14:50:10 -0500
From: Rik van Riel <riel@...riel.com>
To: Borislav Petkov <bp@...en8.de>, Michael Kelley <mhklinux@...look.com>
Cc: x86@...nel.org, linux-kernel@...r.kernel.org, kernel-team@...a.com, 
	dave.hansen@...ux.intel.com, luto@...nel.org, peterz@...radead.org, 
	tglx@...utronix.de, mingo@...hat.com, hpa@...or.com,
 akpm@...ux-foundation.org, 	nadav.amit@...il.com,
 zhengqi.arch@...edance.com, linux-mm@...ck.org
Subject: Re: [PATCH 05/12] x86/mm: add INVLPGB support code

On Thu, 2025-01-02 at 13:42 +0100, Borislav Petkov wrote:
> On Mon, Dec 30, 2024 at 12:53:06PM -0500, Rik van Riel wrote:
> 
> 
> > +{
> > +	u64 rax = addr | flags;
> > +	u32 ecx = (pmd_stride << 31) | extra_count;
> > +	u32 edx = (pcid << 16) | asid;
> > +
> > +	asm volatile("invlpgb" : : "a" (rax), "c" (ecx), "d"
> > (edx));
> 
> No, you do:
> 
> 	/* INVLPGB; supported in binutils >= 2.36. */
>  	asm volatile(".byte 0x0f, 0x01, 0xfe"
> 	...

Sorry, this one fell through the cracks.

I've replaced both of the asm mnemonics with
byte code for the next version of the series.

-- 
All Rights Reversed.

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