[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <53f3803f-c6ef-40db-9794-6c90b37659c1@linaro.org>
Date: Tue, 14 Jan 2025 12:54:43 +0100
From: Daniel Lezcano <daniel.lezcano@...aro.org>
To: Nícolas F. R. A. Prado <nfraprado@...labora.com>,
"Rafael J. Wysocki" <rafael@...nel.org>, Zhang Rui <rui.zhang@...el.com>,
Lukasz Luba <lukasz.luba@....com>, Matthias Brugger
<matthias.bgg@...il.com>,
AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>,
Alexandre Mergnat <amergnat@...libre.com>, Balsam CHIHI <bchihi@...libre.com>
Cc: kernel@...labora.com, linux-pm@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org, Hsin-Te Yuan <yuanhsinte@...omium.org>,
Chen-Yu Tsai <wenst@...omium.org>, Bernhard Rosenkränzer
<bero@...libre.com>, "Rafael J. Wysocki" <rafael.j.wysocki@...el.com>,
stable@...r.kernel.org
Subject: Re: [PATCH RESEND v2 2/5] thermal/drivers/mediatek/lvts: Disable
Stage 3 thermal threshold
On 13/01/2025 14:27, Nícolas F. R. A. Prado wrote:
> The Stage 3 thermal threshold is currently configured during
> the controller initialization to 105 Celsius. From the kernel
> perspective, this configuration is harmful because:
> * The stage 3 interrupt that gets triggered when the threshold is
> crossed is not handled in any way by the IRQ handler, it just gets
> cleared. Besides, the temperature used for stage 3 comes from the
> sensors, and the critical thermal trip points described in the
> Devicetree will already cause a shutdown when crossed (at a lower
> temperature, of 100 Celsius, for all SoCs currently using this
> driver).
> * The only effect of crossing the stage 3 threshold that has been
> observed is that it causes the machine to no longer be able to enter
> suspend. Even if that was a result of a momentary glitch in the
> temperature reading of a sensor (as has been observed on the
> MT8192-based Chromebooks).
>
> For those reasons, disable the Stage 3 thermal threshold configuration.
Does this stage 3 not designed to reset the system ? So the interrupt
line should be attached to the reset line ? (just asking)
--
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
Powered by blists - more mailing lists