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Message-ID: <7df33918-4780-472d-96b5-57566b9a07c1@intel.com>
Date: Wed, 15 Jan 2025 08:38:50 -0800
From: Dave Hansen <dave.hansen@...el.com>
To: Paolo Bonzini <pbonzini@...hat.com>, linux-kernel@...r.kernel.org,
kvm@...r.kernel.org
Cc: kai.huang@...el.com, rick.p.edgecombe@...el.com,
dave.hansen@...ux.intel.com, yan.y.zhao@...el.com,
Sean Christopherson <sean.j.christopherson@...el.com>,
Isaku Yamahata <isaku.yamahata@...el.com>,
Binbin Wu <binbin.wu@...ux.intel.com>, Yuan Yao <yuan.yao@...el.com>
Subject: Re: [PATCH v3 04/14] x86/virt/tdx: Add SEAMCALL wrappers for TDX page
cache management
On 1/15/25 08:09, Paolo Bonzini wrote:
> --- a/arch/x86/include/asm/tdx.h
> +++ b/arch/x86/include/asm/tdx.h
> @@ -137,6 +137,19 @@ struct tdx_vp {
> struct page **tdcx_pages;
> };
>
> +
> +static inline u64 mk_keyed_paddr(u16 hkid, struct page *page)
> +{
> + u64 ret;
> +
> + ret = page_to_phys(page);
> + /* KeyID bits are just above the physical address bits: */
> + ret |= hkid << boot_cpu_data.x86_phys_bits;
> +
> + return ret;
> +
> +}
> +
> u64 tdh_mng_addcx(struct tdx_td *td, struct page *tdcs_page);
Paolo, any chance you could fix up the whitespace goofiness before
applying? It's a super minor thing and I think later patches fix up at
least some of it, but it's a bit wonky.
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