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Message-Id: <20250115012628.1035928-5-pgwipeout@gmail.com>
Date: Wed, 15 Jan 2025 01:26:25 +0000
From: Peter Geis <pgwipeout@...il.com>
To: Heiko Stuebner <heiko@...ech.de>
Cc: zyw@...k-chips.com,
kever.yang@...k-chips.com,
frank.wang@...k-chips.com,
william.wu@...k-chips.com,
wulf@...k-chips.com,
linux-rockchip@...ts.infradead.org,
Peter Geis <pgwipeout@...il.com>,
Alex Bee <knaerzche@...il.com>,
Conor Dooley <conor+dt@...nel.org>,
Diederik de Haas <didi.debian@...ow.org>,
Dragan Simic <dsimic@...jaro.org>,
Johan Jonker <jbx6244@...il.com>,
Jonas Karlman <jonas@...boo.se>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Rob Herring <robh@...nel.org>,
devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org
Subject: [RFC PATCH v1 4/6] arm64: dts: rockchip: add rk3328 usb3 phy node
Add the node for the rk3328 usb3 phy. This node provides a combined usb2
and usb3 phy which are permenantly tied to the dwc3 usb3 controller.
Signed-off-by: Peter Geis <pgwipeout@...il.com>
---
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 39 ++++++++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index 7d992c3c01ce..181a900d41f9 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -903,6 +903,43 @@ u2phy_host: host-port {
};
};
+ usb3phy: usb3-phy@...60000 {
+ compatible = "rockchip,rk3328-usb3phy";
+ reg = <0x0 0xff460000 0x0 0x10000>;
+ clocks = <&cru SCLK_REF_USB3OTG>, <&cru PCLK_USB3PHY_OTG>, <&cru PCLK_USB3PHY_PIPE>;
+ clock-names = "refclk-usb3otg", "usb3phy-otg", "usb3phy-pipe";
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "bvalid", "id", "linestate", "rxdet";
+ resets = <&cru SRST_USB3PHY_U2>,
+ <&cru SRST_USB3PHY_U3>,
+ <&cru SRST_USB3PHY_PIPE>,
+ <&cru SRST_USB3OTG_UTMI>,
+ <&cru SRST_USB3PHY_OTG_P>,
+ <&cru SRST_USB3PHY_PIPE_P>;
+ reset-names = "usb3phy-u2-por", "usb3phy-u3-por",
+ "usb3phy-pipe-mac", "usb3phy-utmi-mac",
+ "usb3phy-utmi-apb", "usb3phy-pipe-apb";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ usb3phy_utmi: utmi-port@...70000 {
+ compatible = "rockchip,rk3328-usb3phy-utmi";
+ reg = <0x0 0xff470000 0x0 0x8000>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ usb3phy_pipe: pipe-port@...78000 {
+ compatible = "rockchip,rk3328-usb3phy-pipe";
+ reg = <0x0 0xff478000 0x0 0x8000>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
+
sdmmc: mmc@...00000 {
compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff500000 0x0 0x4000>;
@@ -1067,6 +1104,8 @@ usbdrd3: usb@...00000 {
clock-names = "ref_clk", "suspend_clk",
"bus_clk";
dr_mode = "otg";
+ phys = <&usb3phy_utmi>, <&usb3phy_pipe>;
+ phy-names = "usb2-phy", "usb3-phy";
phy_type = "utmi_wide";
snps,dis-del-phy-power-chg-quirk;
snps,dis_enblslpm_quirk;
--
2.39.5
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