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Message-ID: <20250115092134.2904773-8-christian.bruel@foss.st.com>
Date: Wed, 15 Jan 2025 10:21:31 +0100
From: Christian Bruel <christian.bruel@...s.st.com>
To: <christian.bruel@...s.st.com>, <bhelgaas@...gle.com>,
<lpieralisi@...nel.org>, <kw@...ux.com>,
<manivannan.sadhasivam@...aro.org>, <robh@...nel.org>,
<krzk+dt@...nel.org>, <conor+dt@...nel.org>,
<mcoquelin.stm32@...il.com>, <alexandre.torgue@...s.st.com>,
<jingoohan1@...il.com>, <p.zabel@...gutronix.de>,
<johan+linaro@...nel.org>, <quic_schintav@...cinc.com>,
<cassel@...nel.org>
CC: <linux-pci@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-stm32@...md-mailman.stormreply.com>,
<linux-arm-kernel@...ts.infradead.org>, <linux-kernel@...r.kernel.org>,
<fabrice.gasnier@...s.st.com>
Subject: [PATCH v3 07/10] arm64: dts: st: add PCIe pinctrl entries in stm32mp25-pinctrl.dtsi
Add PCIe pinctrl entries in stm32mp25-pinctrl.dtsi
init: forces GPIO to low while probing so CLKREQ is low for
phy_init
default: restore the AFMUX after controller probe
Add Analog pins of PCIe to perform power cycle
Signed-off-by: Christian Bruel <christian.bruel@...s.st.com>
---
arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 20 +++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
index 8fdd5f020425..f0d814bc7c60 100644
--- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
@@ -82,6 +82,26 @@ pins {
};
};
+ pcie_pins_a: pcie-0 {
+ pins {
+ pinmux = <STM32_PINMUX('J', 0, AF4)>;
+ bias-disable;
+ };
+ };
+
+ pcie_init_pins_a: pcie-init-0 {
+ pins {
+ pinmux = <STM32_PINMUX('J', 0, GPIO)>;
+ output-low;
+ };
+ };
+
+ pcie_sleep_pins_a: pcie-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('J', 0, ANALOG)>;
+ };
+ };
+
sdmmc1_b4_pins_a: sdmmc1-b4-0 {
pins1 {
pinmux = <STM32_PINMUX('E', 4, AF10)>, /* SDMMC1_D0 */
--
2.34.1
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