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Message-ID: <20250115092134.2904773-10-christian.bruel@foss.st.com>
Date: Wed, 15 Jan 2025 10:21:33 +0100
From: Christian Bruel <christian.bruel@...s.st.com>
To: <christian.bruel@...s.st.com>, <bhelgaas@...gle.com>,
<lpieralisi@...nel.org>, <kw@...ux.com>,
<manivannan.sadhasivam@...aro.org>, <robh@...nel.org>,
<krzk+dt@...nel.org>, <conor+dt@...nel.org>,
<mcoquelin.stm32@...il.com>, <alexandre.torgue@...s.st.com>,
<jingoohan1@...il.com>, <p.zabel@...gutronix.de>,
<johan+linaro@...nel.org>, <quic_schintav@...cinc.com>,
<cassel@...nel.org>
CC: <linux-pci@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-stm32@...md-mailman.stormreply.com>,
<linux-arm-kernel@...ts.infradead.org>, <linux-kernel@...r.kernel.org>,
<fabrice.gasnier@...s.st.com>
Subject: [PATCH v3 09/10] arm64: dts: st: Enable PCIe on the stm32mp257f-ev1 board
Add PCIe RC and EP support on stm32mp257f-ev1 board, and enable RC mode
by default.
Signed-off-by: Christian Bruel <christian.bruel@...s.st.com>
---
arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts
index 1b88485a62a1..f49daa362ebb 100644
--- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts
+++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts
@@ -225,6 +225,24 @@ scmi_vdd_sdcard: regulator@23 {
};
};
+&pcie_ep {
+ pinctrl-names = "default", "init";
+ pinctrl-0 = <&pcie_pins_a>;
+ pinctrl-1 = <&pcie_init_pins_a>;
+ reset-gpios = <&gpioj 8 GPIO_ACTIVE_LOW>;
+ status = "disabled";
+};
+
+&pcie_rc {
+ pinctrl-names = "default", "init", "sleep";
+ pinctrl-0 = <&pcie_pins_a>;
+ pinctrl-1 = <&pcie_init_pins_a>;
+ pinctrl-2 = <&pcie_sleep_pins_a>;
+ reset-gpios = <&gpioj 8 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&gpioh 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ status = "okay";
+};
+
&sdmmc1 {
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc1_b4_pins_a>;
--
2.34.1
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