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Message-ID: <20250115113556.2832282-2-mubin.sayyed@amd.com> Date: Wed, 15 Jan 2025 17:05:54 +0530 From: Mubin Sayyed <mubin.sayyed@....com> To: <krzysztof.kozlowski+dt@...aro.org>, <daniel.lezcano@...aro.org>, <tglx@...utronix.de>, <michal.simek@....com>, <ukleinek@...nel.org> CC: <linux-arm-kernel@...ts.infradead.org>, <linux-kernel@...r.kernel.org>, <linux-pwm@...r.kernel.org>, <git@....com>, Mubin Sayyed <mubin.sayyed@....com> Subject: [PATCH v4 1/3] clocksource: timer-cadence-ttc: Prepare to support TTC PWM Cadence TTC IP supports timer as well as PWM feature.Existing driver supports only timer functionality. PWM feature would be exposed through separate file which is going to be added in drivers/pwm directory. Move #defines related to TTC IP to timer-cadence-ttc.h, so that they can be re-used by PWM part of the driver. Signed-off-by: Mubin Sayyed <mubin.sayyed@....com> --- Changes for v4: - New patch --- drivers/clocksource/timer-cadence-ttc.c | 30 +-------------------- include/linux/timer-cadence-ttc.h | 35 +++++++++++++++++++++++++ 2 files changed, 36 insertions(+), 29 deletions(-) create mode 100644 include/linux/timer-cadence-ttc.h diff --git a/drivers/clocksource/timer-cadence-ttc.c b/drivers/clocksource/timer-cadence-ttc.c index b8a1cf59b9d6..2f33d4c40153 100644 --- a/drivers/clocksource/timer-cadence-ttc.c +++ b/drivers/clocksource/timer-cadence-ttc.c @@ -18,6 +18,7 @@ #include <linux/sched_clock.h> #include <linux/module.h> #include <linux/of_platform.h> +#include <linux/timer-cadence-ttc.h> /* * This driver configures the 2 16/32-bit count-up timers as follows: @@ -34,35 +35,6 @@ * obtained from device tree. The pre-scaler of 32 is used. */ -/* - * Timer Register Offset Definitions of Timer 1, Increment base address by 4 - * and use same offsets for Timer 2 - */ -#define TTC_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */ -#define TTC_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */ -#define TTC_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */ -#define TTC_INTR_VAL_OFFSET 0x24 /* Interval Count Reg, RW */ -#define TTC_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO */ -#define TTC_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW */ - -#define TTC_CNT_CNTRL_DISABLE_MASK 0x1 - -#define TTC_CLK_CNTRL_CSRC_MASK (1 << 5) /* clock source */ -#define TTC_CLK_CNTRL_PSV_MASK 0x1e -#define TTC_CLK_CNTRL_PSV_SHIFT 1 - -/* - * Setup the timers to use pre-scaling, using a fixed value for now that will - * work across most input frequency, but it may need to be more dynamic - */ -#define PRESCALE_EXPONENT 11 /* 2 ^ PRESCALE_EXPONENT = PRESCALE */ -#define PRESCALE 2048 /* The exponent must match this */ -#define CLK_CNTRL_PRESCALE ((PRESCALE_EXPONENT - 1) << 1) -#define CLK_CNTRL_PRESCALE_EN 1 -#define CNT_CNTRL_RESET (1 << 4) - -#define MAX_F_ERR 50 - /** * struct ttc_timer - This definition defines local timer structure * diff --git a/include/linux/timer-cadence-ttc.h b/include/linux/timer-cadence-ttc.h new file mode 100644 index 000000000000..d938991371e5 --- /dev/null +++ b/include/linux/timer-cadence-ttc.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +/* + *Copyright (c) 2025 Advanced Micro Devices, Inc. + */ + +/* + * Timer Register Offset Definitions of Timer 1, Increment base address by 4 + * and use same offsets for Timer 2 + */ +#define TTC_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */ +#define TTC_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */ +#define TTC_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */ +#define TTC_INTR_VAL_OFFSET 0x24 /* Interval Count Reg, RW */ +#define TTC_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO */ +#define TTC_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW */ + +#define TTC_CNT_CNTRL_DISABLE_MASK 0x1 + +#define TTC_CLK_CNTRL_CSRC_MASK (1 << 5) /* clock source */ +#define TTC_CLK_CNTRL_PSV_MASK 0x1e +#define TTC_CLK_CNTRL_PSV_SHIFT 1 + +/* + * Setup the timers to use pre-scaling, using a fixed value for now that will + * work across most input frequency, but it may need to be more dynamic + */ +#define PRESCALE_EXPONENT 11 /* 2 ^ PRESCALE_EXPONENT = PRESCALE */ +#define PRESCALE 2048 /* The exponent must match this */ +#define CLK_CNTRL_PRESCALE ((PRESCALE_EXPONENT - 1) << 1) +#define CLK_CNTRL_PRESCALE_EN 1 +#define CNT_CNTRL_RESET (1 << 4) + +#define MAX_F_ERR 50 + -- 2.25.1
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