linux-kernel - [PATCH v2 0/7] riscv: pmu: Add support for Control Transfer Records Ext.

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Message-Id: <20250116230955.867152-1-rkanwal@rivosinc.com>
Date: Thu, 16 Jan 2025 23:09:48 +0000
From: Rajnesh Kanwal <rkanwal@...osinc.com>
To: linux-kernel@...r.kernel.org,
	linux-riscv@...ts.infradead.org
Cc: linux-perf-users@...r.kernel.org,
	adrian.hunter@...el.com,
	alexander.shishkin@...ux.intel.com,
	ajones@...tanamicro.com,
	anup@...infault.org,
	acme@...nel.org,
	atishp@...osinc.com,
	beeman@...osinc.com,
	brauner@...nel.org,
	conor@...nel.org,
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	irogers@...gle.com,
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	james.clark@....com,
	renyu.zj@...ux.alibaba.com,
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	will@...nel.org,
	kaiwenxue1@...il.com,
	vincent.chen@...ive.com,
	Rajnesh Kanwal <rkanwal@...osinc.com>
Subject: [PATCH v2 0/7] riscv: pmu: Add support for Control Transfer Records Ext.

This series enables Control Transfer Records extension support on riscv
architecture. This extension is similar to Arch LBR in x86 and BRBE in ARM.
The Extension has been ratified and the latest release can be found here [0]

CTR extension depends on both the implementation of S-mode and Sscsrind
extension v1.0.0 [1]. CTR access ctrsource, ctrtartget and ctrdata CSRs using
sscsrind extension.

The series is based on Smcdeleg/Ssccfg counter delegation extension [2]
patches [3]. CTR itself doesn't depend on counter delegation support. This
rebase is basically to include the Smcsrind patches.

The last patch is in the perf tool to allow processing 256 entries. Without
this perf seems to consider that sample as corrupted and discards it.

Here is the link to a quick guide [4] to setup and run a basic perf demo on
Linux to use CTR Ext.

Qemu patches can be found here:
https://github.com/rajnesh-kanwal/qemu/tree/b4/ctr_upstream_v5

Opensbi patch can be found here:
https://github.com/rajnesh-kanwal/opensbi/tree/ctr_upstream_v2

Linux kernel patches can be found here:
https://github.com/rajnesh-kanwal/linux/tree/b4/ctr_upstream_v2

[0]: https://github.com/riscv/riscv-control-transfer-records/releases/tag/v1.0
[1]: https://github.com/riscvarchive/riscv-indirect-csr-access/releases/tag/v1.0.0
[2]: https://github.com/riscvarchive/riscv-smcdeleg-ssccfg/releases/tag/v1.0.0
[3]: https://lore.kernel.org/lkml/20250114-counter_delegation-v2-0-8ba74cdb851b@rivosinc.com/
[4]: https://github.com/rajnesh-kanwal/linux/wiki/Running-CTR-basic-demo-on-QEMU-RISC%E2%80%90V-Virt-machine

Rajnesh Kanwal (7):
  perf: Increase the maximum number of samples to 256.
  riscv: pmu: Add Control transfer records CSR definations.
  riscv: Add Control Transfer Records extension parsing
  dt-bindings: riscv: add Sxctr ISA extension description
  riscv: pmu: Add infrastructure for Control Transfer Record
  riscv: pmu: Add driver for Control Transfer Records Ext.
  riscv: pmu: Integrate CTR Ext support in riscv_pmu_dev driver

 .../devicetree/bindings/riscv/extensions.yaml |  14 +
 MAINTAINERS                                   |   1 +
 arch/riscv/include/asm/csr.h                  |  83 +++
 arch/riscv/include/asm/hwcap.h                |   4 +
 arch/riscv/kernel/cpufeature.c                |   2 +
 drivers/perf/Kconfig                          |  11 +
 drivers/perf/Makefile                         |   1 +
 drivers/perf/riscv_ctr.c                      | 608 ++++++++++++++++++
 drivers/perf/riscv_pmu_common.c               |  23 +-
 drivers/perf/riscv_pmu_dev.c                  |  82 +++
 drivers/perf/riscv_pmu_legacy.c               |   2 +
 include/linux/perf/riscv_pmu.h                |  55 ++
 tools/perf/util/machine.c                     |  21 +-
 13 files changed, 898 insertions(+), 9 deletions(-)
 create mode 100644 drivers/perf/riscv_ctr.c

-- 
2.34.1