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Message-Id: <20250116230955.867152-5-rkanwal@rivosinc.com>
Date: Thu, 16 Jan 2025 23:09:52 +0000
From: Rajnesh Kanwal <rkanwal@...osinc.com>
To: linux-kernel@...r.kernel.org,
linux-riscv@...ts.infradead.org
Cc: linux-perf-users@...r.kernel.org,
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Rajnesh Kanwal <rkanwal@...osinc.com>
Subject: [PATCH v2 4/7] dt-bindings: riscv: add Sxctr ISA extension description
Add the S[m|s]ctr ISA extension description.
Signed-off-by: Rajnesh Kanwal <rkanwal@...osinc.com>
---
.../devicetree/bindings/riscv/extensions.yaml | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index 848354e3048f..8322503f0773 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -167,6 +167,13 @@ properties:
extension allows other ISA extension to use indirect CSR access
mechanism in M-mode.
+ - const: smctr
+ description: |
+ The standard Smctr supervisor-level extension for the machine mode
+ to enable recording limited branch history in a register-accessible
+ internal core storage. Smctr depend on both the implementation of
+ S-mode and the Sscsrind extension.
+
- const: sscsrind
description: |
The standard Sscsrind supervisor-level extension extends the
@@ -193,6 +200,13 @@ properties:
and mode-based filtering as ratified at commit 01d1df0 ("Add ability
to manually trigger workflow. (#2)") of riscv-count-overflow.
+ - const: ssctr
+ description: |
+ The standard Ssctr supervisor-level extension enables recording of
+ limited branch history in a register-accessible internal core
+ storage. Ssctr depend on both the implementation of S-mode and the
+ Sscsrind extension.
+
- const: ssnpm
description: |
The standard Ssnpm extension for next-mode pointer masking as
--
2.34.1
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