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Message-Id: <20250116232118.2694169-7-sean.anderson@linux.dev>
Date: Thu, 16 Jan 2025 18:21:16 -0500
From: Sean Anderson <sean.anderson@...ux.dev>
To: Mark Brown <broonie@...nel.org>,
Michal Simek <michal.simek@....com>,
linux-spi@...r.kernel.org
Cc: Jinjie Ruan <ruanjinjie@...wei.com>,
linux-arm-kernel@...ts.infradead.org,
Amit Kumar Mahapatra <amit.kumar-mahapatra@....com>,
linux-kernel@...r.kernel.org,
Miquel Raynal <miquel.raynal@...tlin.com>,
Sean Anderson <sean.anderson@...ux.dev>
Subject: [PATCH 6/7] spi: zynqmp-gqspi: Support GPIO chip selects
GPIO chipselects use the traditional SPU API instead of the SPIMEM API.
Implement it with transfer_one and set_cs (for non-GPIO chipselects). At
the moment we only support half-duplex transfers, which is good enough
to access SPI flashes.
Signed-off-by: Sean Anderson <sean.anderson@...ux.dev>
---
drivers/spi/spi-zynqmp-gqspi.c | 83 ++++++++++++++++++++++++++++++++++
1 file changed, 83 insertions(+)
diff --git a/drivers/spi/spi-zynqmp-gqspi.c b/drivers/spi/spi-zynqmp-gqspi.c
index 9823d710c4d6..efd01e06b77a 100644
--- a/drivers/spi/spi-zynqmp-gqspi.c
+++ b/drivers/spi/spi-zynqmp-gqspi.c
@@ -528,6 +528,15 @@ static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high)
dev_err(xqspi->dev, "Chip select timed out\n");
}
+static void zynqmp_qspi_set_cs(struct spi_device *qspi, bool is_high)
+{
+ struct zynqmp_qspi *xqspi = spi_controller_get_devdata(qspi->controller);
+
+ mutex_lock(&xqspi->op_lock);
+ zynqmp_qspi_chipselect(qspi, is_high);
+ mutex_unlock(&xqspi->op_lock);
+}
+
/**
* zynqmp_qspi_selectspimode - Selects SPI mode - x1 or x2 or x4.
* @xqspi: xqspi is a pointer to the GQSPI instance
@@ -1271,6 +1280,75 @@ static int zynqmp_qspi_exec_op(struct spi_mem *mem,
return err;
}
+static int zynqmp_qspi_transfer_one(struct spi_controller *ctlr,
+ struct spi_device *spi,
+ struct spi_transfer *transfer)
+{
+ struct zynqmp_qspi *xqspi = spi_controller_get_devdata(ctlr);
+ unsigned long timeout;
+ u32 genfifoentry;
+ u32 mask = 0;
+ int ret;
+
+ dev_dbg(xqspi->dev, "xfer %u/%u %u\n", transfer->tx_nbits,
+ transfer->rx_nbits, transfer->len);
+
+ if (transfer->tx_nbits && transfer->rx_nbits)
+ return -EOPNOTSUPP;
+
+ guard(mutex)(&xqspi->op_lock);
+ zynqmp_qspi_config_op(xqspi, transfer->speed_hz, spi->mode);
+ if (spi_get_csgpiod(spi, 0)) {
+ if (ctlr == xqspi->lower) {
+ xqspi->genfifobus = GQSPI_GENFIFO_BUS_LOWER;
+ } else {
+ WARN_ON_ONCE(ctlr != xqspi->upper);
+ xqspi->genfifobus = GQSPI_GENFIFO_BUS_UPPER;
+ }
+ xqspi->genfifocs = 0;
+ }
+ genfifoentry = xqspi->genfifocs | xqspi->genfifobus;
+
+ reinit_completion(&xqspi->data_completion);
+ if (transfer->tx_nbits) {
+ xqspi->txbuf = transfer->tx_buf;
+ xqspi->rxbuf = NULL;
+ xqspi->bytes_to_transfer = transfer->len;
+ xqspi->bytes_to_receive = 0;
+ zynqmp_qspi_write_op(xqspi, transfer->tx_nbits, genfifoentry);
+ mask = GQSPI_IER_TXEMPTY_MASK | GQSPI_IER_GENFIFOEMPTY_MASK |
+ GQSPI_IER_TXNOT_FULL_MASK;
+ timeout = zynqmp_qspi_timeout(xqspi, transfer->tx_nbits,
+ transfer->len);
+ } else {
+ xqspi->txbuf = NULL;
+ xqspi->rxbuf = transfer->rx_buf;
+ xqspi->bytes_to_transfer = 0;
+ xqspi->bytes_to_receive = transfer->len;
+ ret = zynqmp_qspi_read_op(xqspi, transfer->rx_nbits,
+ genfifoentry);
+ if (ret)
+ return ret;
+
+ if (xqspi->mode != GQSPI_MODE_DMA)
+ mask = GQSPI_IER_GENFIFOEMPTY_MASK |
+ GQSPI_IER_RXNEMPTY_MASK | GQSPI_IER_RXEMPTY_MASK;
+ timeout = zynqmp_qspi_timeout(xqspi, transfer->rx_nbits,
+ transfer->len);
+ }
+
+ zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
+ zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
+ GQSPI_CFG_START_GEN_FIFO_MASK);
+ if (mask)
+ zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST, mask);
+ else
+ zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_EN_OFST,
+ GQSPI_QSPIDMA_DST_I_EN_DONE_MASK);
+
+ return zynqmp_qspi_wait(xqspi, timeout);
+}
+
static const struct dev_pm_ops zynqmp_qspi_dev_pm_ops = {
SET_RUNTIME_PM_OPS(zynqmp_runtime_suspend,
zynqmp_runtime_resume, NULL)
@@ -1318,6 +1396,7 @@ zynqmp_qspi_alloc_split(struct zynqmp_qspi *xqspi, const char *name)
return ERR_PTR(-ENOMEM);
ctlr->dev.of_node = np;
+ ctlr->max_native_cs = 1;
if (of_property_read_u32(np, "num-cs", &num_cs))
ctlr->num_chipselect = GQSPI_DEFAULT_NUM_CS;
else
@@ -1337,11 +1416,15 @@ static int zynqmp_qspi_register_ctlr(struct zynqmp_qspi *xqspi,
spi_controller_set_devdata(ctlr, xqspi);
ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD |
SPI_TX_DUAL | SPI_TX_QUAD;
+ ctlr->flags = SPI_CONTROLLER_HALF_DUPLEX;
ctlr->max_speed_hz = xqspi->speed_hz;
ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
ctlr->mem_ops = &zynqmp_qspi_mem_ops;
ctlr->setup = zynqmp_qspi_setup_op;
+ ctlr->set_cs = zynqmp_qspi_set_cs;
+ ctlr->transfer_one = zynqmp_qspi_transfer_one;
ctlr->auto_runtime_pm = true;
+ ctlr->use_gpio_descriptors = true;
ret = devm_spi_register_controller(xqspi->dev, ctlr);
if (ret)
--
2.35.1.1320.gc452695387.dirty
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