linux-kernel - Re: [PATCH v4] arm64: dts: qcom: Add coresight node for SM8650

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <cchokycqaigagaoqbfb5bxt6zq5dd4le7bpirl4lu5em7byqv5@cpjgz5dbsdxq>
Date: Fri, 17 Jan 2025 12:17:02 +0200
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Yuanfang Zhang <quic_yuanfang@...cinc.com>
Cc: neil.armstrong@...aro.org, Bjorn Andersson <andersson@...nel.org>, 
	Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, kernel@...cinc.com, 
	linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v4] arm64: dts: qcom: Add coresight node for SM8650

On Fri, Jan 17, 2025 at 04:20:01PM +0800, Yuanfang Zhang wrote:
> 
> 
> On 1/16/2025 11:57 PM, neil.armstrong@...aro.org wrote:
> > Hi,
> > 
> > On 07/01/2025 09:48, Yuanfang Zhang wrote:
> >> Add coresight components: Funnel, ETE and ETF for SM8650.
> >>
> >> Signed-off-by: Yuanfang Zhang <quic_yuanfang@...cinc.com>
> >> ---
> >> Changes in v4:
> >> - Re-sort these nodes by address.
> >> - Link to v3: https://lore.kernel.org/r/20250103-sm8650-cs-dt-v3-1-759a3f6a3cc8@quicinc.com
> >>
> >> Changes in v3:
> >> - Move ete0 and funnel-ete to /.
> >> - Update coding style.
> >> - Link to v2: https://lore.kernel.org/r/20241210-sm8650-cs-dt-v2-1-cf24c6c9bddc@quicinc.com
> >>
> >> Changes in v2:
> >> - Update compatible for funnel and etf.
> >> - remove unnecessary property: reg-names and arm,primecell-periphid.
> >> - Link to v1: https://lore.kernel.org/r/20241210-sm8650-cs-dt-v1-1-269693451584@quicinc.com
> >> ---
> >>   arch/arm64/boot/dts/qcom/sm8650.dtsi | 166 +++++++++++++++++++++++++++++++++++
> >>   1 file changed, 166 insertions(+)
> >>
> >> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
> >> index 25e47505adcb790d09f1d2726386438487255824..49d6567fbd2e68b66b517d8d9180c7443f8bf611 100644
> >> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
> >> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
> >> @@ -365,6 +365,40 @@ cluster_sleep_1: cluster-sleep-1 {
> >>           };
> >>       };
> >>   +    ete0 {
> >> +        compatible = "arm,embedded-trace-extension";
> >> +
> >> +        cpu = <&cpu0>;
> >> +
> >> +        out-ports {
> >> +            port {
> >> +                ete0_out_funnel_ete: endpoint {
> >> +                    remote-endpoint = <&funnel_ete_in_ete0>;
> >> +                };
> >> +            };
> >> +        };
> >> +    };
> > 
> > Why only the cpu0 ete has been added ?
> > 
> > And why are the other components (TPDA, TPDM, STM, CTI...) missing ?
> > 
> > Neil
> > 
> At present, only ete0 is used, and other components can be added later if need.

Please describe the hardware, not the usecase. If there are other trace
cells, please add them.

-- 
With best wishes
Dmitry