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Message-ID: <20250120-expert-fox-of-argument-c4dcde@krzk-bin>
Date: Mon, 20 Jan 2025 08:45:47 +0100
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Sergio Paracuellos <sergio.paracuellos@...il.com>
Cc: linux-clk@...r.kernel.org, sboyd@...nel.org, mturquette@...libre.com,
tsbogend@...ha.franken.de, robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
matthias.bgg@...il.com, angelogioacchino.delregno@...labora.com, p.zabel@...gutronix.de,
linux-mips@...r.kernel.org, devicetree@...r.kernel.org, yangshiji66@...look.com,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 1/6] dt-bindings: clock: add clock and reset
definitions for Ralink SoCs
On Sun, Jan 19, 2025 at 04:44:42PM +0100, Sergio Paracuellos wrote:
> +#endif /* _DT_BINDINGS_CLK_MTMIPS_H */
> diff --git a/include/dt-bindings/reset/mediatek,mtmips-sysc.h b/include/dt-bindings/reset/mediatek,mtmips-sysc.h
> new file mode 100644
> index 000000000000..1bc6024b1f22
> --- /dev/null
> +++ b/include/dt-bindings/reset/mediatek,mtmips-sysc.h
> @@ -0,0 +1,152 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * Author: Sergio Paracuellos <sergio.paracuellos@...il.com>
> + */
> +
> +#ifndef _DT_BINDINGS_RST_MTMIPS_H
> +#define _DT_BINDINGS_RST_MTMIPS_H
> +
> +/* Ralink RT-2880 resets */
> +
> +#define RT2880_RST_SYS 0
> +#define RT2880_RST_I2C 9
> +#define RT2880_RST_FE 18
These do not look correct. I understood from previous discussions that
driver relies on these for its internal operation. It looks true for
clocks, but does not look true here at all. This is register bit passed
to the hardware (and I explicitly mentioned last time: that I expect
these not being register bits passed to hardware).
None of the resets are bindings - these are just hardware constants.
Best regards,
Krzysztof
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