linux-kernel - Re: [PATCH 2/2] arm64: dts: qcom: Add cpu scaling clock node

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Message-ID: <608afa23-ca4e-48dd-b929-4466560a7e61@quicinc.com>
Date: Mon, 20 Jan 2025 16:27:59 +0530
From: Taniya Das <quic_tdas@...cinc.com>
To: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
CC: Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio
	<konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski
	<krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Ajit Pandey
	<quic_ajipan@...cinc.com>,
        Imran Shaik <quic_imrashai@...cinc.com>,
        "Jagadeesh Kona" <quic_jkona@...cinc.com>,
        <linux-arm-msm@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>, <quic_manafm@...cinc.com>
Subject: Re: [PATCH 2/2] arm64: dts: qcom: Add cpu scaling clock node



On 1/20/2025 4:06 PM, Dmitry Baryshkov wrote:
> On Mon, 20 Jan 2025 at 12:34, Taniya Das <quic_tdas@...cinc.com> wrote:
>>
>>
>>
>> On 1/20/2025 2:16 PM, Dmitry Baryshkov wrote:
>>>>> This doesn't follow the bindings, does it?
>>>> I will add and re-use the closest target compatible.
>>>>
>>>>>> +          reg = <0 0x18323000 0 0x1400>,
>>>>>> +                <0 0x18325800 0 0x1400>;
>>>>>> +          reg-names = "freq-domain0", "freq-domain1";
>>>>>> +
>>>>>> +          clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
>>>>>> +          clock-names = "xo", "alternate";
>>>>> Are the DCVSH interrupts?
>>>>>
>>>> This target does not have DCVSH interrupts directly connected to the
>>>> CPUFREQ-HW.
>>> So, does it require a separate LMH driver, like the one used for sdm845?
>>
>> I will check how it is handled on QCS615 as it is closer to SC7180 and I
>> didn't see any LMH handling there as well.
> 
> At least sm6150-thermal.dtsi declares two LMH blocks.

QCS615 also has 2 LMH blocks, but the handling of interrupts will be 
done from the LMH driver, integration with CPUFREQ-HW driver is still 
under evaluation.

-- 
Thanks & Regards,
Taniya Das.