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Message-ID: <9910bc4a-2d60-43a8-a14e-05bbb30d0011@quicinc.com>
Date: Mon, 20 Jan 2025 20:02:49 +0800
From: Ziqi Chen <quic_ziqichen@...cinc.com>
To: Manivannan Sadhasivam <mani@...nel.org>
CC: <quic_cang@...cinc.com>, <bvanassche@....org>, <beanhuo@...ron.com>,
<avri.altman@....com>, <junwoo80.lee@...sung.com>,
<martin.petersen@...cle.com>, <quic_nguyenb@...cinc.com>,
<quic_nitirawa@...cinc.com>, <quic_rampraka@...cinc.com>,
<linux-scsi@...r.kernel.org>,
Manivannan Sadhasivam
<manivannan.sadhasivam@...aro.org>,
"James E.J. Bottomley"
<James.Bottomley@...senPartnership.com>,
"open list:UNIVERSAL FLASH STORAGE
HOST CONTROLLER DRIVER..." <linux-arm-msm@...r.kernel.org>,
open list
<linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 2/8] scsi: ufs: qcom: Pass target_freq to clk scale pre
and post change
Hi Mani,
Thanks for you review~
On 1/19/2025 3:22 PM, Manivannan Sadhasivam wrote:
> On Thu, Jan 16, 2025 at 05:11:43PM +0800, Ziqi Chen wrote:
>> From: Can Guo <quic_cang@...cinc.com>
>>
>> If OPP V2 is used, devfreq clock scaling may scale clock amongst more than
>> two freqs.
>
> Same comment as previous patch.
>
please see my response in previous patch.
>> In the case of scaling up, the devfreq may decide to scale the
>> clock to an intermidiate freq base on load, but the clock scale up pre
>> change operation uses settings for the max clock freq unconditionally. Fix
>> it by passing the target_freq to clock scale up pre change so that the
>> correct settings for the target_freq can be used.
>>
>> In the case of scaling down, the clock scale down post change operation
>> is doing fine, because it reads the actual clock rate to tell freq, but to
>> keep symmetry with clock scale up pre change operation, just use the
>> target_freq instead of reading clock rate.
>>
>> Co-developed-by: Ziqi Chen <quic_ziqichen@...cinc.com>
>> Signed-off-by: Ziqi Chen <quic_ziqichen@...cinc.com>
>> Signed-off-by: Can Guo <quic_cang@...cinc.com>
>> ---
>> drivers/ufs/host/ufs-qcom.c | 23 ++++++++++++-----------
>> 1 file changed, 12 insertions(+), 11 deletions(-)
>>
>> diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
>> index b6eef975dc46..1e8a23eb8c13 100644
>> --- a/drivers/ufs/host/ufs-qcom.c
>> +++ b/drivers/ufs/host/ufs-qcom.c
>> @@ -97,7 +97,7 @@ static const struct __ufs_qcom_bw_table {
>> };
>>
>> static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host);
>> -static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, bool is_scale_up);
>> +static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, unsigned long freq);
>>
>> static struct ufs_qcom_host *rcdev_to_ufs_host(struct reset_controller_dev *rcd)
>> {
>> @@ -524,7 +524,7 @@ static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
>> return -EINVAL;
>> }
>>
>> - err = ufs_qcom_set_core_clk_ctrl(hba, true);
>> + err = ufs_qcom_set_core_clk_ctrl(hba, ULONG_MAX);
>> if (err)
>> dev_err(hba->dev, "cfg core clk ctrl failed\n");
>> /*
>> @@ -1231,7 +1231,7 @@ static int ufs_qcom_set_clk_40ns_cycles(struct ufs_hba *hba,
>> return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CORE_CLK_40NS_CYCLES), reg);
>> }
>>
>> -static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, bool is_scale_up)
>> +static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, unsigned long freq)
>> {
>> struct ufs_qcom_host *host = ufshcd_get_variant(hba);
>> struct list_head *head = &hba->clk_list_head;
>> @@ -1245,10 +1245,11 @@ static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, bool is_scale_up)
>> !strcmp(clki->name, "core_clk_unipro")) {
>> if (!clki->max_freq)
>> cycles_in_1us = 150; /* default for backwards compatibility */
>> - else if (is_scale_up)
>> + else if (freq == ULONG_MAX)
>> cycles_in_1us = ceil(clki->max_freq, (1000 * 1000));
>> else
>> - cycles_in_1us = ceil(clk_get_rate(clki->clk), (1000 * 1000));
>> + cycles_in_1us = ceil(freq, (1000 * 1000));
>
> Consider switching to HZ_PER_MHZ in a separate patch later
Sure, Thanks for suggestion, will update in next version.
>
> - Mani
-Ziqi
>
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