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Message-ID: <226df026-f3c8-4a89-a0a2-66ed3e744109@quicinc.com>
Date: Mon, 20 Jan 2025 20:08:00 +0800
From: Ziqi Chen <quic_ziqichen@...cinc.com>
To: Manivannan Sadhasivam <mani@...nel.org>
CC: <quic_cang@...cinc.com>, <bvanassche@....org>, <beanhuo@...ron.com>,
<avri.altman@....com>, <junwoo80.lee@...sung.com>,
<martin.petersen@...cle.com>, <quic_nguyenb@...cinc.com>,
<quic_nitirawa@...cinc.com>, <quic_rampraka@...cinc.com>,
<linux-scsi@...r.kernel.org>, Alim Akhtar <alim.akhtar@...sung.com>,
"James
E.J. Bottomley" <James.Bottomley@...senPartnership.com>,
Peter Wang
<peter.wang@...iatek.com>,
Manivannan Sadhasivam
<manivannan.sadhasivam@...aro.org>,
Andrew Halaney <ahalaney@...hat.com>,
Maramaina Naresh <quic_mnaresh@...cinc.com>,
open list
<linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 5/8] scsi: ufs: core: Enable multi-level gear scaling
Hi Mani,
Thanks for your comment~
On 1/19/2025 3:48 PM, Manivannan Sadhasivam wrote:
> On Thu, Jan 16, 2025 at 05:11:46PM +0800, Ziqi Chen wrote:
>> From: Can Guo <quic_cang@...cinc.com>
>>
>> With OPP V2 enabled, devfreq can scale clocks amongst multiple frequency
>> plans. However, the gear speed is only toggled between min and max during
>> clock scaling. Enable multi-level gear scaling by mapping clock frequencies
>> to gear speeds, so that when devfreq scales clock frequencies we can put
>> the UFS link at the appropraite gear speeds accordingly.
>>
>> Co-developed-by: Ziqi Chen <quic_ziqichen@...cinc.com>
>> Signed-off-by: Ziqi Chen <quic_ziqichen@...cinc.com>
>> Signed-off-by: Can Guo <quic_cang@...cinc.com>
>> ---
>> drivers/ufs/core/ufshcd.c | 46 ++++++++++++++++++++++++++++++---------
>> 1 file changed, 36 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c
>> index 8d295cc827cc..839bc23aeda0 100644
>> --- a/drivers/ufs/core/ufshcd.c
>> +++ b/drivers/ufs/core/ufshcd.c
>> @@ -1308,16 +1308,28 @@ static int ufshcd_wait_for_doorbell_clr(struct ufs_hba *hba,
>> /**
>> * ufshcd_scale_gear - scale up/down UFS gear
>> * @hba: per adapter instance
>> + * @target_gear: target gear to scale to
>> * @scale_up: True for scaling up gear and false for scaling down
>> *
>> * Return: 0 for success; -EBUSY if scaling can't happen at this time;
>> * non-zero for any other errors.
>> */
>> -static int ufshcd_scale_gear(struct ufs_hba *hba, bool scale_up)
>> +static int ufshcd_scale_gear(struct ufs_hba *hba, u32 target_gear, bool scale_up)
>> {
>> int ret = 0;
>> struct ufs_pa_layer_attr new_pwr_info;
>>
>> + if (target_gear) {
>> + memcpy(&new_pwr_info, &hba->pwr_info,
>> + sizeof(struct ufs_pa_layer_attr));
>> +
>> + new_pwr_info.gear_tx = target_gear;
>> + new_pwr_info.gear_rx = target_gear;
>> +
>> + goto do_pmc;
>
> goto config_pwr_mode;
>
Ok, Thanks for your suggestion, I will change it in next version.
>> + }
>> +
>> + /* Legacy gear scaling, in case vops_freq_to_gear_speed() is not implemented */
>> if (scale_up) {
>> memcpy(&new_pwr_info, &hba->clk_scaling.saved_pwr_info,
>> sizeof(struct ufs_pa_layer_attr));
>> @@ -1338,6 +1350,7 @@ static int ufshcd_scale_gear(struct ufs_hba *hba, bool scale_up)
>> }
>> }
>>
>> +do_pmc:
>> /* check if the power mode needs to be changed or not? */
>> ret = ufshcd_config_pwr_mode(hba, &new_pwr_info);
>> if (ret)
>> @@ -1408,15 +1421,19 @@ static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba, int err, bool sc
>> static int ufshcd_devfreq_scale(struct ufs_hba *hba, unsigned long freq,
>> bool scale_up)
>> {
>> + u32 old_gear = hba->pwr_info.gear_rx;
>> + u32 new_gear = 0;
>> int ret = 0;
>>
>> + ufshcd_vops_freq_to_gear_speed(hba, freq, &new_gear);
>> +
>> ret = ufshcd_clock_scaling_prepare(hba, 1 * USEC_PER_SEC);
>> if (ret)
>> return ret;
>>
>> /* scale down the gear before scaling down clocks */
>> if (!scale_up) {
>> - ret = ufshcd_scale_gear(hba, false);
>> + ret = ufshcd_scale_gear(hba, new_gear, false);
>> if (ret)
>> goto out_unprepare;
>> }
>> @@ -1424,13 +1441,13 @@ static int ufshcd_devfreq_scale(struct ufs_hba *hba, unsigned long freq,
>> ret = ufshcd_scale_clks(hba, freq, scale_up);
>> if (ret) {
>> if (!scale_up)
>> - ufshcd_scale_gear(hba, true);
>> + ufshcd_scale_gear(hba, old_gear, true);
>> goto out_unprepare;
>> }
>>
>> /* scale up the gear after scaling up clocks */
>> if (scale_up) {
>> - ret = ufshcd_scale_gear(hba, true);
>> + ret = ufshcd_scale_gear(hba, new_gear, true);
>> if (ret) {
>> ufshcd_scale_clks(hba, hba->devfreq->previous_freq,
>> false);
>> @@ -1723,6 +1740,8 @@ static ssize_t ufshcd_clkscale_enable_store(struct device *dev,
>> struct device_attribute *attr, const char *buf, size_t count)
>> {
>> struct ufs_hba *hba = dev_get_drvdata(dev);
>> + struct ufs_clk_info *clki;
>> + unsigned long freq;
>> u32 value;
>> int err = 0;
>>
>> @@ -1746,14 +1765,21 @@ static ssize_t ufshcd_clkscale_enable_store(struct device *dev,
>>
>> if (value) {
>> ufshcd_resume_clkscaling(hba);
>> - } else {
>> - ufshcd_suspend_clkscaling(hba);
>> - err = ufshcd_devfreq_scale(hba, ULONG_MAX, true);
>> - if (err)
>> - dev_err(hba->dev, "%s: failed to scale clocks up %d\n",
>> - __func__, err);
>> + goto out_rel;
>> }
>>
>> + clki = list_first_entry(&hba->clk_list_head, struct ufs_clk_info, list);
>> + freq = clki->max_freq;
>> +
>> + ufshcd_suspend_clkscaling(hba);
>> + err = ufshcd_devfreq_scale(hba, freq, true);
>> + if (err)
>> + dev_err(hba->dev, "%s: failed to scale clocks up %d\n",
>> + __func__, err);
>> + else
>> + hba->clk_scaling.target_freq = freq;
>> +
>
> Just noticed that the 'clkscale_enable', 'clkgate_{delay_ms}/enable' sysfs
> attributes have no ABI documentation. Please add them also in a separate patch.
Ok, I will update it in next version.
> > - Mani
>
-Ziqi
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