linux-kernel - Re: [PATCH 8/8] ARM: dts: msm: Use Operation Points V2 for UFS on SM8650

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <872d2183-b255-4d4d-b7e6-acdaa2737172@quicinc.com>
Date: Mon, 20 Jan 2025 20:13:15 +0800
From: Ziqi Chen <quic_ziqichen@...cinc.com>
To: <neil.armstrong@...aro.org>, <quic_cang@...cinc.com>, <bvanassche@....org>,
        <mani@...nel.org>, <beanhuo@...ron.com>, <avri.altman@....com>,
        <junwoo80.lee@...sung.com>, <martin.petersen@...cle.com>,
        <quic_nguyenb@...cinc.com>, <quic_nitirawa@...cinc.com>,
        <quic_rampraka@...cinc.com>
CC: <linux-scsi@...r.kernel.org>, Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>,
        "open list:ARM/QUALCOMM SUPPORT" <linux-arm-msm@...r.kernel.org>,
        "open
 list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
	<devicetree@...r.kernel.org>,
        open list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 8/8] ARM: dts: msm: Use Operation Points V2 for UFS on
 SM8650


On 1/16/2025 5:24 PM, neil.armstrong@...aro.org wrote:
> Hi,
> 
> On 16/01/2025 10:11, Ziqi Chen wrote:
>> Use Operation Points V2 for UFS on SM8650 so that multi-level
>> clock/gear scaling can be possible.
> 
> 
> I've already sent a similar one at 
> https://lore.kernel.org/all/20250115-topic-sm8x50-upstream-dt-icc-update-v1-10-eaa8b10e2af7@linaro.org/
> 
> Neil
> 

Hi Neil,

Thank you for reminder , I will withdraw this patch in next version.

- Ziqi

>>
>> Co-developed-by: Can Guo <quic_cang@...cinc.com>
>> Signed-off-by: Can Guo <quic_cang@...cinc.com>
>> Signed-off-by: Ziqi Chen <quic_ziqichen@...cinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/sm8650.dtsi | 51 +++++++++++++++++++++++-----
>>   1 file changed, 43 insertions(+), 8 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi 
>> b/arch/arm64/boot/dts/qcom/sm8650.dtsi
>> index 01ac3769ffa6..5466f1217f64 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
>> @@ -2557,18 +2557,11 @@ ufs_mem_hc: ufs@...4000 {
>>                         "tx_lane0_sync_clk",
>>                         "rx_lane0_sync_clk",
>>                         "rx_lane1_sync_clk";
>> -            freq-table-hz = <100000000 403000000>,
>> -                    <0 0>,
>> -                    <0 0>,
>> -                    <100000000 403000000>,
>> -                    <100000000 403000000>,
>> -                    <0 0>,
>> -                    <0 0>,
>> -                    <0 0>;
>>               resets = <&gcc GCC_UFS_PHY_BCR>;
>>               reset-names = "rst";
>> +            operating-points-v2 = <&ufs_opp_table>;
>>               interconnects = <&aggre1_noc MASTER_UFS_MEM 
>> QCOM_ICC_TAG_ALWAYS
>>                        &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
>>                       <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
>> @@ -2590,6 +2583,48 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
>>               #reset-cells = <1>;
>>               status = "disabled";
>> +
>> +            ufs_opp_table: opp-table {
>> +                       compatible = "operating-points-v2";
>> +                       // LOW_SVS
>> +                       opp-100000000 {
>> +                               opp-hz = /bits/ 64 <100000000>,
>> +                                       /bits/ 64 <0>,
>> +                                       /bits/ 64 <0>,
>> +                                       /bits/ 64 <100000000>,
>> +                                       /bits/ 64 <0>,
>> +                                       /bits/ 64 <0>,
>> +                                       /bits/ 64 <0>,
>> +                                       /bits/ 64 <0>;
>> +                               required-opps = <&rpmhpd_opp_low_svs>;
>> +                       };
>> +
>> +                       // SVS
>> +                       opp-201500000 {
>> +                               opp-hz = /bits/ 64 <201500000>,
>> +                                       /bits/ 64 <0>,
>> +                                       /bits/ 64 <0>,
>> +                                       /bits/ 64 <201500000>,
>> +                                       /bits/ 64 <0>,
>> +                                       /bits/ 64 <0>,
>> +                                       /bits/ 64 <0>,
>> +                                       /bits/ 64 <0>;
>> +                               required-opps = <&rpmhpd_opp_svs>;
>> +                       };
>> +
>> +                       // NOM/TURBO
>> +                       opp-403000000 {
>> +                               opp-hz = /bits/ 64 <403000000>,
>> +                                       /bits/ 64 <0>,
>> +                                       /bits/ 64 <0>,
>> +                                       /bits/ 64 <403000000>,
>> +                                       /bits/ 64 <0>,
>> +                                       /bits/ 64 <0>,
>> +                                       /bits/ 64 <0>,
>> +                                       /bits/ 64 <0>;
>> +                               required-opps = <&rpmhpd_opp_nom>;
>> +                       };
>> +               };
>>           };
>>           ice: crypto@...8000 {
>