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Message-ID: <20250121204758.GR674319@ziepe.ca>
Date: Tue, 21 Jan 2025 16:47:58 -0400
From: Jason Gunthorpe <jgg@...pe.ca>
To: Alex Williamson <alex.williamson@...hat.com>
Cc: Wencheng Yang <east.moutain.yang@...il.com>,
	Joerg Roedel <joro@...tes.org>,
	Suravee Suthikulpanit <suravee.suthikulpanit@....com>,
	Will Deacon <will@...nel.org>, Robin Murphy <robin.murphy@....com>,
	iommu@...ts.linux.dev, linux-kernel@...r.kernel.org,
	kvm@...r.kernel.org
Subject: Re: [PATCH v2] drviers/iommu/amd: support P2P access through IOMMU
 when SME is enabled

On Tue, Jan 21, 2025 at 08:34:43AM -0700, Alex Williamson wrote:

> This description is unclear to me.  As others have noted, we probably
> need to look at whether the flag should be automatically applied by the
> kernel.  We certainly know in the vfio IOMMU layer whether we're
> mapping a page or a pfnmap.  

It is not page or pfnmap.. When vfio is using follow_pte() it should
extract information from the PTE and then relay it to the IOMMU. The
iommu page table and the CPU page table should have the same PTE
flags.

So, a pte that is pgprot_cached() should be IOMMU_CACHE, otherwise
IOMMU_MMIO.

The encrypted bit in the PTE should be mapped to some new
IOMMU_ENCRYPTED.

I suspect AMD has created a troublesome issue that IOMMU_CACHE
conditionally implies encrypted depending on their platform features
(meaning cachable decrypted is impossible). Arguably a higher level
should be deciding this and the iommu page table code should simply
follow IOMMU_ENCRYPTED always.

That might be something for later, but I would note it :\

> In any case, we're in the process of phasing out the vfio type1
> IOMMU backend for iommufd, so whatever the implementation, and
> especially if there's a uapi component, it needs to be implemented
> in iommufd first. 

Since iommufd won't be using follow_pte() it will have to get this
meta information from the FD, eg through DMABUf, and there is a huge
thread on how to go about doing that..

There should be no uapi component.

Jason

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