linux-kernel - Re: [GIT PULL] x86/cleanups for v6.14

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Message-ID: <Z49OBcRezoW3P9RZ@gmail.com>
Date: Tue, 21 Jan 2025 08:34:29 +0100
From: Ingo Molnar <mingo@...nel.org>
To: Linus Torvalds <torvalds@...ux-foundation.org>
Cc: linux-kernel@...r.kernel.org, the arch/x86 maintainers <x86@...nel.org>
Subject: Re: [GIT PULL] x86/cleanups for v6.14


* Ingo Molnar <mingo@...nel.org> wrote:

> Linus,
> 
> Please pull the latest x86/cleanups Git tree from:
> 
>    git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86-cleanups-2025-01-21
> 
>    # HEAD: 0094014be0cd75273ef7f2934c17fb8cffd4db6e x86/ioapic: Remove a stray tab in the IO-APIC type string
> 
> Miscellaneous x86 cleanups and typo fixes, and also the removal
> of the "disablelapic" boot parameter.

Merge note: if you've pulled x86/sev from Boris already, then there 
will be a new conflict in arch/x86/include/asm/cpufeatures.h due to 
overlapping (but compatible) changes to the same lines of code.

My conflict resolution is below, for reference.

Thanks,

	Ingo

=======================>

    Merge branch 'x86/cleanups' into tmp.tmp
    
     Conflicts:
            arch/x86/include/asm/cpufeatures.h
    
    Signed-off-by: Ingo Molnar <mingo@...nel.org>

diff --cc arch/x86/include/asm/cpufeatures.h
index 8b55685255d6,09e1e54676f4..9746e75a1866
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@@ -443,18 -443,15 +443,18 @@@
  #define X86_FEATURE_SPEC_CTRL_SSBD	(18*32+31) /* Speculative Store Bypass Disable */
  
  /* AMD-defined memory encryption features, CPUID level 0x8000001f (EAX), word 19 */
- #define X86_FEATURE_SME			(19*32+ 0) /* "sme" AMD Secure Memory Encryption */
- #define X86_FEATURE_SEV			(19*32+ 1) /* "sev" AMD Secure Encrypted Virtualization */
+ #define X86_FEATURE_SME			(19*32+ 0) /* "sme" Secure Memory Encryption */
+ #define X86_FEATURE_SEV			(19*32+ 1) /* "sev" Secure Encrypted Virtualization */
  #define X86_FEATURE_VM_PAGE_FLUSH	(19*32+ 2) /* VM Page Flush MSR is supported */
- #define X86_FEATURE_SEV_ES		(19*32+ 3) /* "sev_es" AMD Secure Encrypted Virtualization - Encrypted State */
- #define X86_FEATURE_SEV_SNP		(19*32+ 4) /* "sev_snp" AMD Secure Encrypted Virtualization - Secure Nested Paging */
+ #define X86_FEATURE_SEV_ES		(19*32+ 3) /* "sev_es" Secure Encrypted Virtualization - Encrypted State */
+ #define X86_FEATURE_SEV_SNP		(19*32+ 4) /* "sev_snp" Secure Encrypted Virtualization - Secure Nested Paging */
  #define X86_FEATURE_V_TSC_AUX		(19*32+ 9) /* Virtual TSC_AUX */
- #define X86_FEATURE_SME_COHERENT	(19*32+10) /* AMD hardware-enforced cache coherency */
- #define X86_FEATURE_DEBUG_SWAP		(19*32+14) /* "debug_swap" AMD SEV-ES full debug state swap support */
+ #define X86_FEATURE_SME_COHERENT	(19*32+10) /* hardware-enforced cache coherency */
+ #define X86_FEATURE_DEBUG_SWAP		(19*32+14) /* "debug_swap" SEV-ES full debug state swap support */
 +#define X86_FEATURE_RMPREAD		(19*32+21) /* RMPREAD instruction */
 +#define X86_FEATURE_SEGMENTED_RMP	(19*32+23) /* Segmented RMP support */
  #define X86_FEATURE_SVSM		(19*32+28) /* "svsm" SVSM present */
 +#define X86_FEATURE_HV_INUSE_WR_ALLOWED	(19*32+30) /* Allow Write to in-use hypervisor-owned pages */
  
  /* AMD-defined Extended Feature 2 EAX, CPUID level 0x80000021 (EAX), word 20 */
  #define X86_FEATURE_NO_NESTED_DATA_BP	(20*32+ 0) /* No Nested Data Breakpoints */