linux-kernel - Re: [PATCH] ARM: cacheinfo fix format field mask

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Message-ID: <Z4-s9UHBJZx9APeE@shell.armlinux.org.uk>
Date: Tue, 21 Jan 2025 14:19:33 +0000
From: "Russell King (Oracle)" <linux@...linux.org.uk>
To: Geert Uytterhoeven <geert@...ux-m68k.org>
Cc: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>,
	Linus Walleij <linus.walleij@...aro.org>,
	Sudeep Holla <sudeep.holla@....com>,
	Ard Biesheuvel <ardb@...nel.org>, Arnd Bergmann <arnd@...db.de>,
	linux-arm-kernel@...ts.infradead.org,
	linux-samsung-soc@...r.kernel.org, linux-kernel@...r.kernel.org,
	Marek Szyprowski <m.szyprowski@...sung.com>,
	Linux-Renesas <linux-renesas-soc@...r.kernel.org>
Subject: Re: [PATCH] ARM: cacheinfo fix format field mask

On Tue, Jan 21, 2025 at 03:12:13PM +0100, Geert Uytterhoeven wrote:
> Hi Dmitry,
> 
> Thanks for your patch!
> 
> On Wed, Jan 15, 2025 at 12:11 PM Dmitry Baryshkov
> <dmitry.baryshkov@...aro.org> wrote:
> > Fix C&P error left unnoticed during the reviews. The FORMAT field spans
> > over bits 29-31, not 24-27 of the CTR register.
> 
> Please add
> 
>     This causes a warning on e.g. Cortex-A8 and Cortex-A9:
> 
>         WARNING: CPU: 0 PID: 0 at arch/arm/kernel/cacheinfo.c:43
> cache_line_size+0x84/0x94
> 
> so people find this patch when looking up the warning.
> 
> > Fixes: a9ff94477836 ("ARM: 9433/2: implement cacheinfo support")
> > Reported-by: Marek Szyprowski <m.szyprowski@...sung.com>
> > Closes: https://lore.kernel.org/linux-arm-msm/01515ea0-c6f0-479f-9da5-764d9ee79ed6@samsung.com/
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
> 
> This fixes the warning on Cortex-A8/A9, so
> Tested-by: Geert Uytterhoeven <geert+renesas@...der.be>
> 
> Note that this changes HWalign on Cortex-A9 (various Renesas SoCs,
> with 1, 2, or 4 CPU cores):
> 
>     -SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=<N>, Nodes=1
>     +SLUB: HWalign=32, Order=0-3, MinObjects=0, CPUs=<N>, Nodes=1
> 
> On Cortex-A8 (BeagleBone Black, i.e. AM335x), it changes HWalign,
> and causes a warning message:
> 
>     -SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
>     +SLUB: HWalign=16, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
>      ...
>     +cacheinfo: Unable to detect cache hierarchy for CPU 0
> 

Also, has this been tested on CPUs that don't implement the cache type
register?

-- 
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