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Message-ID: <fc17525c-1543-42cf-93b4-2b2fb9d409ce@intel.com>
Date: Wed, 22 Jan 2025 11:42:52 -0800
From: Jacob Keller <jacob.e.keller@...el.com>
To: Christian Marangi <ansuelsmth@...il.com>, Lorenzo Bianconi
<lorenzo@...nel.org>, Felix Fietkau <nbd@....name>, Sean Wang
<sean.wang@...iatek.com>, Andrew Lunn <andrew+netdev@...n.ch>, "David S.
Miller" <davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>, "Jakub
Kicinski" <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>, Matthias
Brugger <matthias.bgg@...il.com>, AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>,
<linux-arm-kernel@...ts.infradead.org>, <linux-mediatek@...ts.infradead.org>,
<netdev@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [net PATCH v2] net: airoha: Fix wrong GDM4 register definition
On 1/20/2025 7:41 AM, Christian Marangi wrote:
> Fix wrong GDM4 register definition, in Airoha SDK GDM4 is defined at
> offset 0x2400 but this doesn't make sense as it does conflict with the
> CDM4 that is in the same location.
>
The wording of this first paragraph is a bit odd. I think the "Fix wrong
GDMA4 register definition" part is redundant with the title and makes
this feel like a run-on sentence. Anyways, not worth a re-roll.
Reviewed-by: Jacob Keller <jacob.e.keller@...el.com>
> Following the pattern where each GDM base is at the FWD_CFG, currently
> GDM4 base offset is set to 0x2500. This is correct but REG_GDM4_FWD_CFG
> and REG_GDM4_SRC_PORT_SET are still using the SDK reference with the
> 0x2400 offset. Fix these 2 define by subtracting 0x100 to each register
> to reflect the real address location.
>
> Fixes: 23020f049327 ("net: airoha: Introduce ethernet support for EN7581 SoC")
> Signed-off-by: Christian Marangi <ansuelsmth@...il.com>
> Acked-by: Lorenzo Bianconi <lorenzo@...nel.org>
> ---
> Changes v2:
> - Target correct file (fix wrong downstream branch used)
>
> drivers/net/ethernet/mediatek/airoha_eth.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/net/ethernet/mediatek/airoha_eth.c b/drivers/net/ethernet/mediatek/airoha_eth.c
> index 415d784de741..09f448f29124 100644
> --- a/drivers/net/ethernet/mediatek/airoha_eth.c
> +++ b/drivers/net/ethernet/mediatek/airoha_eth.c
> @@ -266,11 +266,11 @@
> #define REG_GDM3_FWD_CFG GDM3_BASE
> #define GDM3_PAD_EN_MASK BIT(28)
>
> -#define REG_GDM4_FWD_CFG (GDM4_BASE + 0x100)
> +#define REG_GDM4_FWD_CFG GDM4_BASE
> #define GDM4_PAD_EN_MASK BIT(28)
> #define GDM4_SPORT_OFFSET0_MASK GENMASK(11, 8)
>
> -#define REG_GDM4_SRC_PORT_SET (GDM4_BASE + 0x33c)
> +#define REG_GDM4_SRC_PORT_SET (GDM4_BASE + 0x23c)
> #define GDM4_SPORT_OFF2_MASK GENMASK(19, 16)
> #define GDM4_SPORT_OFF1_MASK GENMASK(15, 12)
> #define GDM4_SPORT_OFF0_MASK GENMASK(11, 8)
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