lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <09bd2f04-96d6-4dba-92ee-22ccbd7f584f@alliedtelesis.co.nz>
Date: Wed, 22 Jan 2025 23:02:14 +0000
From: Chris Packham <Chris.Packham@...iedtelesis.co.nz>
To: Andrew Lunn <andrew@...n.ch>
CC: Sander Vanheule <sander@...nheule.net>, "lee@...nel.org" <lee@...nel.org>,
	"robh@...nel.org" <robh@...nel.org>, "krzk+dt@...nel.org"
	<krzk+dt@...nel.org>, "conor+dt@...nel.org" <conor+dt@...nel.org>,
	"andrew+netdev@...n.ch" <andrew+netdev@...n.ch>, "davem@...emloft.net"
	<davem@...emloft.net>, "edumazet@...gle.com" <edumazet@...gle.com>,
	"kuba@...nel.org" <kuba@...nel.org>, "pabeni@...hat.com" <pabeni@...hat.com>,
	"tsbogend@...ha.franken.de" <tsbogend@...ha.franken.de>,
	"hkallweit1@...il.com" <hkallweit1@...il.com>, "linux@...linux.org.uk"
	<linux@...linux.org.uk>, "markus.stockhausen@....de"
	<markus.stockhausen@....de>, "devicetree@...r.kernel.org"
	<devicetree@...r.kernel.org>, "linux-kernel@...r.kernel.org"
	<linux-kernel@...r.kernel.org>, "netdev@...r.kernel.org"
	<netdev@...r.kernel.org>, "linux-mips@...r.kernel.org"
	<linux-mips@...r.kernel.org>
Subject: Re: [PATCH v4 4/4] net: mdio: Add RTL9300 MDIO driver

Hi Andrew,

On 23/01/2025 10:47, Andrew Lunn wrote:
>> I believe the POLL_SEL configuration actually affects an internal port
>> polling unit. From the datasheets I have it seems pretty configurable, you
>> can tell it which phy registers to poll and what values indicate link
>> up/down (the defaults are conveniently setup to match the Realtek PHYs).
> You need to disable this. The linux PHY driver is driving the PHY, and
> the hardware has no idea what Linux is doing. Say the driver has
> changed the page to read a temperature sensor, when the switch does a
> poll. Rather than reading the link status, it gets some random value
> from the page containing the temperature sensor.

There's a mask that can be set via a register that can disable polling 
for a port. The trick will be deciding when to do so.

For C45 PHYs I think it's fine as the register space is so large that 
paging isn't really used (the only time I've seen it is in the vendor 
MMD). The PPU does seem to have some knowledge of paging for C22 but as 
far as I understand the page select register varies vendor to vendor and 
I can't see any way of telling it so it probably just uses whatever page 
select register that realtek use in their PHYs.

So I _think_ the PPU is OK. What might be a bit more tricky is the other 
way round where Linux is doing something involving changing pages and 
reading registers, there would need to be some kind mechanism that masks 
the port out of the PPU for the duration of the whole transaction.


>
> 	Andrew

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ