lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <f6fa8949-6c49-4aa2-8b3d-1ce23ca73f96@linaro.org>
Date: Wed, 22 Jan 2025 02:23:03 +0200
From: Vladimir Zapolskiy <vladimir.zapolskiy@...aro.org>
To: Bryan O'Donoghue <bryan.odonoghue@...aro.org>,
 Robert Foss <rfoss@...nel.org>, Todor Tomov <todor.too@...il.com>,
 Mauro Carvalho Chehab <mchehab@...nel.org>
Cc: linux-media@...r.kernel.org, linux-arm-msm@...r.kernel.org,
 linux-kernel@...r.kernel.org, Depeng Shao <quic_depengs@...cinc.com>,
 Vikram Sharma <quic_vikramsa@...cinc.com>
Subject: Re: [PATCH 5/7] media: qcom: camss: Add support for 3ph CSIPHY write
 settle delay

On 1/20/25 17:47, Bryan O'Donoghue wrote:
> Currently we have an s32 value called delay which has been inherited from
> the CamX code for PHY init. This unused value relates to a post-write delay
> latching time.
> 
> In the silicon test-bench which provides the basis for the CamX code the
> write settle times are specified in nanoseconds.
> 
> In the upstream kernel we currently take no notice of the delay value and
> use all zero in any case.
> 
> Nanosecond granularity timing from the perspective of the kernel is total
> overkill, however for some PHY init sequences introduction of a settle
> delay has a use.
> 
> Add support to the 3ph init sequence for microsecond level delay. A
> readback of written data would probably accomplish the same thing but,
> since the PHY init sequences in the wild provide a delay value - we can
> just add support here for that delay and consume the values given.
> 
> Generally these delays are probably not necessary but, they do speak to a
> theoretical delay that silicon test-benches utilise and therefore are
> worthwhile to replicate if the given PHY init sequence has the data.
> 
> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@...aro.org>

Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@...aro.org>

--
Best wishes,
Vladimir

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ