[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID:
<BM1PR01MB254564DCF4004C3E60177331FEE12@BM1PR01MB2545.INDPRD01.PROD.OUTLOOK.COM>
Date: Wed, 22 Jan 2025 21:51:05 +0800
From: Chen Wang <unicorn_wang@...look.com>
To: Inochi Amaoto <inochiama@...il.com>, Chen Wang <unicornxw@...il.com>,
u.kleine-koenig@...libre.com, aou@...s.berkeley.edu, arnd@...db.de,
conor+dt@...nel.org, guoren@...nel.org, inochiama@...look.com,
krzk+dt@...nel.org, palmer@...belt.com, paul.walmsley@...ive.com,
robh@...nel.org, tglx@...utronix.de, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org,
chao.wei@...hgo.com, xiaoguang.xing@...hgo.com, fengchun.li@...hgo.com,
samuel.holland@...ive.com, christophe.jaillet@...adoo.fr
Subject: Re: [PATCH v3 1/3] dt-bindings: interrupt-controller: Add Sophgo
SG2042 MSI
On 2025/1/20 10:42, Inochi Amaoto wrote:
> On Wed, Jan 15, 2025 at 02:33:23PM +0800, Chen Wang wrote:
[......]
>> + reg:
>> + items:
>> + - description: msi doorbell address
>> + - description: clear register
>> +
>> + reg-names:
>> + items:
>> + - const: doorbell
>> + - const: clr
> please reverse the items order, the clr addr is more suitable
> as the MMIO device address when writing device node. doorbeel
> address is just a IO address and can not be seen from CPU.
I find dtbcheck will report error if order is switched.
On SG2042, address of doorbell is ahead of clr.
>> +
>> + msi-controller: true
>> +
>> + msi-ranges:
>> + maxItems: 1
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - reg-names
>> + - msi-controller
>> + - msi-ranges
>> +
>> +unevaluatedProperties: false
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/interrupt-controller/irq.h>
>> + msi-controller@...00000 {
>> + compatible = "sophgo,sg2042-msi";
>> + reg = <0x30000000 0x4>, <0x30000008 0x4>;
>> + reg-names = "doorbell", "clr";
>> + msi-controller;
>> + msi-ranges = <&plic 64 IRQ_TYPE_LEVEL_HIGH 32>;
>> + interrupt-parent = <&plic>;
>> + };
>> --
>> 2.34.1
>>
>>
>> _______________________________________________
>> linux-riscv mailing list
>> linux-riscv@...ts.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-riscv
Powered by blists - more mailing lists