lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <CAEvtbuviH+bGNz1dEPKXTbBD582hu=us4aiFyo=zHqfRw7+YRQ@mail.gmail.com>
Date: Wed, 22 Jan 2025 16:38:31 +0100
From: Stefan Schmidt <stefan.schmidt@...aro.org>
To: Taniya Das <quic_tdas@...cinc.com>
Cc: Bjorn Andersson <andersson@...nel.org>, Michael Turquette <mturquette@...libre.com>, 
	Stephen Boyd <sboyd@...nel.org>, Ajit Pandey <quic_ajipan@...cinc.com>, 
	Imran Shaik <quic_imrashai@...cinc.com>, Jagadeesh Kona <quic_jkona@...cinc.com>, 
	linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org, 
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH 0/3] Add support to reconfigure PLL

Hello Taniya,

On Mon, 13 Jan 2025 at 18:27, Taniya Das <quic_tdas@...cinc.com> wrote:
>
> During boot-up, there is a possibility that the PLL configuration might
> be missed even after invoking pll_configure() from the clock controller
> probe. This is often due to the PLL being connected to rail or rails
> that are in an OFF state and current clock controller also cannot vote
> on multiple rails. As a result, the PLL may be enabled with suboptimal
> settings, leading to functional issues.
>
> The PLL configuration, now part of clk_alpha_pll, can be reused to
> reconfigure the PLL to a known good state before scaling for frequency.
> The 'clk_alpha_pll_reconfigure()' can be updated to support more PLLs
> in future.
>
> The IRIS driver support added
> https://lore.kernel.org/all/20241212-qcom-video-iris-v9-0-e8c2c6bd4041@quicinc.com/
> observes the pll latch warning during boot up due to the dependency of
> the PLL not in good state, thus add config support for SM8550 Video
> clock controller PLLs.
>
> Signed-off-by: Taniya Das <quic_tdas@...cinc.com>
> ---
> Taniya Das (3):
>       clk: qcom: clk-alpha-pll: Integrate PLL configuration into PLL structure
>       clk: qcom: clk-alpha-pll: Add support to reconfigure PLL
>       clk: qcom: videocc-sm8550: Update the pll config for Video PLLs
>
>  drivers/clk/qcom/clk-alpha-pll.c  | 30 ++++++++++++++++++++++++++++++
>  drivers/clk/qcom/clk-alpha-pll.h  |  2 ++
>  drivers/clk/qcom/videocc-sm8550.c |  2 ++
>  3 files changed, 34 insertions(+)
> ---
> base-commit: 37136bf5c3a6f6b686d74f41837a6406bec6b7bc
> change-id: 20250113-support-pll-reconfigure-9a9cbb43a90b

I tested the full patchset on my X Elite Dell XPS and can confirm that
the Lucid PLL latch failed warning is gone when using the iris driver.

Tested-by: Stefan Schmidt <stefan.schmidt@...aro.org> # x1e80100 (Dell
XPS 13 9345)

regards
Stefan Schmidt

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ