linux-kernel - Re: [PATCH] clk: renesas: r9a07g043: Fix HP clock source for RZ/Five SoC

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Message-ID: <CAMuHMdVP8LrqAYK7sPJqiB+Fagk=CrhSwX1CixKOxoiGgyDEoQ@mail.gmail.com>
Date: Thu, 23 Jan 2025 21:29:10 +0100
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Prabhakar <prabhakar.csengg@...il.com>
Cc: Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, 
	linux-renesas-soc@...r.kernel.org, linux-clk@...r.kernel.org, 
	linux-kernel@...r.kernel.org, Biju Das <biju.das.jz@...renesas.com>, 
	Fabrizio Castro <fabrizio.castro.jz@...esas.com>, 
	Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>, stable@...r.kernel.org
Subject: Re: [PATCH] clk: renesas: r9a07g043: Fix HP clock source for RZ/Five SoC

Hi Prabhakar,

Thanks for your patch!

On Wed, Jan 22, 2025 at 11:08 AM Prabhakar <prabhakar.csengg@...il.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
>
> According to the Rev.1.20 hardware manual for the RZ/Five SoC, the clock
> source for HP is derived from PLL6 divided by 2. This patch corrects the
> implementation by configuring HP as a fixed clock source instead of a MUX.
>
> The `CPG_PL6_ETH_SSEL` register, which is available on the RZ/G2UL SoC, is
> not present on the RZ/Five SoC, necessitating this change.

While the register is not documented to exist, it reads back the same
default value as on RZ/G2UL, selecting the right parent that does exist.

> Fixes: 95d48d270305ad2c ("clk: renesas: r9a07g043: Add support for RZ/Five SoC")
> Cc: stable@...r.kernel.org
> Reported-by: Hien Huynh <hien.huynh.px@...esas.com>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>

> --- a/drivers/clk/renesas/r9a07g043-cpg.c
> +++ b/drivers/clk/renesas/r9a07g043-cpg.c
> @@ -138,7 +138,11 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = {
>         DEF_DIV("P2", R9A07G043_CLK_P2, CLK_PLL3_DIV2_4_2, DIVPL3A, dtable_1_32),
>         DEF_FIXED("M0", R9A07G043_CLK_M0, CLK_PLL3_DIV2_4, 1, 1),
>         DEF_FIXED("ZT", R9A07G043_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1),
> +#ifdef CONFIG_ARM64
>         DEF_MUX("HP", R9A07G043_CLK_HP, SEL_PLL6_2, sel_pll6_2),

When building with W=1 on non-ARM64:

    error: ‘sel_pll6_2’ defined but not used

so sel_pll6_2 [] needs to be protected by an #ifdef too (or __maybe_unused,
but the rest of the file uses __ifdef).

> +#else

The rest of the file uses:

    #endif
    #ifdef CONFIG_RISCV

instead of #else, so please use the same construct for consistency.

> +       DEF_FIXED("HP", R9A07G043_CLK_HP, CLK_PLL6_250, 1, 1),
> +#endif
>         DEF_FIXED("SPI0", R9A07G043_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2),
>         DEF_FIXED("SPI1", R9A07G043_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4),
>         DEF_SD_MUX("SD0", R9A07G043_CLK_SD0, SEL_SDHI0, SEL_SDHI0_STS, sel_sdhi,

The actual change LGTM.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds