linux-kernel - [PATCH 11/20] perf/x86/intel: Setup PEBS constraints base on counter & pdist map

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-Id: <20250123140721.2496639-12-dapeng1.mi@linux.intel.com>
Date: Thu, 23 Jan 2025 14:07:12 +0000
From: Dapeng Mi <dapeng1.mi@...ux.intel.com>
To: Peter Zijlstra <peterz@...radead.org>,
	Ingo Molnar <mingo@...hat.com>,
	Arnaldo Carvalho de Melo <acme@...nel.org>,
	Namhyung Kim <namhyung@...nel.org>,
	Ian Rogers <irogers@...gle.com>,
	Adrian Hunter <adrian.hunter@...el.com>,
	Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
	Kan Liang <kan.liang@...ux.intel.com>,
	Andi Kleen <ak@...ux.intel.com>,
	Eranian Stephane <eranian@...gle.com>
Cc: linux-kernel@...r.kernel.org,
	linux-perf-users@...r.kernel.org,
	Dapeng Mi <dapeng1.mi@...el.com>,
	Dapeng Mi <dapeng1.mi@...ux.intel.com>
Subject: [PATCH 11/20] perf/x86/intel: Setup PEBS constraints base on counter & pdist map

arch-PEBS provides CPUIDs to enumerate which counters support PEBS
sampling and precise distribution PEBS sampling. Thus PEBS constraints
can be dynamically configured base on these counter and precise
distribution bitmap instead of defining them statically.

Signed-off-by: Dapeng Mi <dapeng1.mi@...ux.intel.com>
---
 arch/x86/events/intel/core.c | 20 ++++++++++++++++++++
 arch/x86/events/intel/ds.c   |  1 +
 2 files changed, 21 insertions(+)

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 7775e1e1c1e9..0f1be36113fa 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -3728,6 +3728,7 @@ intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
 			    struct perf_event *event)
 {
 	struct event_constraint *c1, *c2;
+	struct pmu *pmu = event->pmu;
 
 	c1 = cpuc->event_constraint[idx];
 
@@ -3754,6 +3755,25 @@ intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
 		c2->weight = hweight64(c2->idxmsk64);
 	}
 
+	if (x86_pmu.arch_pebs && event->attr.precise_ip) {
+		u64 pebs_cntrs_mask;
+		u64 cntrs_mask;
+
+		if (event->attr.precise_ip >= 3)
+			pebs_cntrs_mask = hybrid(pmu, arch_pebs_cap).pdists;
+		else
+			pebs_cntrs_mask = hybrid(pmu, arch_pebs_cap).counters;
+
+		cntrs_mask = hybrid(pmu, fixed_cntr_mask64) << INTEL_PMC_IDX_FIXED |
+			     hybrid(pmu, cntr_mask64);
+
+		if (pebs_cntrs_mask != cntrs_mask) {
+			c2 = dyn_constraint(cpuc, c2, idx);
+			c2->idxmsk64 &= pebs_cntrs_mask;
+			c2->weight = hweight64(c2->idxmsk64);
+		}
+	}
+
 	return c2;
 }
 
diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index 2f2c6b7c801b..a573ce0e576a 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -2941,6 +2941,7 @@ static void __init intel_arch_pebs_init(void)
 	x86_pmu.pebs_buffer_size = PEBS_BUFFER_SIZE;
 	x86_pmu.drain_pebs = intel_pmu_drain_arch_pebs;
 	x86_pmu.pebs_capable = ~0ULL;
+	x86_pmu.flags |= PMU_FL_PEBS_ALL;
 }
 
 /*
-- 
2.40.1