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Message-ID: <9206e44c-da4f-4bdb-850f-fac511f4ddc7@quicinc.com>
Date: Thu, 23 Jan 2025 12:05:04 +0530
From: Manikanta Mylavarapu <quic_mmanikan@...cinc.com>
To: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
CC: <lpieralisi@...nel.org>, <kw@...ux.com>, <robh@...nel.org>,
<bhelgaas@...gle.com>, <krzk+dt@...nel.org>, <conor+dt@...nel.org>,
<andersson@...nel.org>, <konradybcio@...nel.org>,
<linux-arm-msm@...r.kernel.org>, <linux-pci@...r.kernel.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<quic_srichara@...cinc.com>, <quic_varada@...cinc.com>
Subject: Re: [PATCH v2 2/3] arm64: dts: qcom: ipq5424: Add PCIe PHYs and
controller nodes
On 1/19/2025 6:15 PM, Manivannan Sadhasivam wrote:
> On Wed, Jan 15, 2025 at 12:17:46PM +0530, Manikanta Mylavarapu wrote:
>> Add PCIe0, PCIe1, PCIe2, PCIe3 (and corresponding PHY) devices
>> found on IPQ5424 platform. The PCIe0 & PCIe1 are 1-lane Gen3
>> host whereas PCIe2 & PCIe3 are 2-lane Gen3 host.
>>
>> Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@...cinc.com>
>> ---
>> Changes in V2:
>> - Add a newline above status in all pcie nodes.
>> - Changed reg-names to a vertical list format in
>> all pcie nodes.
>> - Updated the order of pcie phy clocks in gcc node,
>> move the <0> entry to the end of clock list.
>> - Updated the ranges property in the soc@0 node to align
>> with the linux-next tip.
>>
>> arch/arm64/boot/dts/qcom/ipq5424.dtsi | 500 +++++++++++++++++++++++++-
>> 1 file changed, 496 insertions(+), 4 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
>> index 7034d378b1ef..708cd709a495 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
>> @@ -9,6 +9,7 @@
>> #include <dt-bindings/interrupt-controller/arm-gic.h>
>> #include <dt-bindings/clock/qcom,ipq5424-gcc.h>
>> #include <dt-bindings/reset/qcom,ipq5424-gcc.h>
>> +#include <dt-bindings/interconnect/qcom,ipq5424.h>
>> #include <dt-bindings/gpio/gpio.h>
>>
>> / {
>> @@ -152,6 +153,98 @@ soc@0 {
>> #size-cells = <2>;
>> ranges = <0 0 0 0 0x10 0>;
>>
>> + pcie0_phy: phy@...00 {
>> + compatible = "qcom,ipq5424-qmp-gen3x1-pcie-phy",
>> + "qcom,ipq9574-qmp-gen3x1-pcie-phy";
>> + reg = <0 0x00084000 0 0x2000>;
>
> Use 0x0 for consistency. Here and everywhere.
>
>> + clocks = <&gcc GCC_PCIE0_AUX_CLK>,
>> + <&gcc GCC_PCIE0_AHB_CLK>,
>> + <&gcc GCC_PCIE0_PIPE_CLK>;
>> + clock-names = "aux", "cfg_ahb", "pipe";
>> +
>> + assigned-clocks = <&gcc GCC_PCIE0_AUX_CLK>;
>> + assigned-clock-rates = <20000000>;
>> +
>> + resets = <&gcc GCC_PCIE0_PHY_BCR>,
>> + <&gcc GCC_PCIE0PHY_PHY_BCR>;
>> + reset-names = "phy", "common";
>> +
>> + #clock-cells = <0>;
>> + clock-output-names = "gcc_pcie0_pipe_clk_src";
>> +
>> + #phy-cells = <0>;
>> + status = "disabled";
>> + };
>
> [...]
>
>> + pcie3: pcie@...00000 {
>> + compatible = "qcom,pcie-ipq5424",
>> + "qcom,pcie-ipq9574";
>
> Put it in previous line itself.
>
>> + reg = <0 0x40000000 0 0xf1d>,
>> + <0 0x40000f20 0 0xa8>,
>> + <0 0x40001000 0 0x1000>,
>> + <0 0x000f8000 0 0x3000>,
>> + <0 0x40100000 0 0x1000>;
>> + reg-names = "dbi",
>> + "elbi",
>> + "atu",
>> + "parf",
>> + "config";
>> + device_type = "pci";
>> + linux,pci-domain = <3>;
>> + bus-range = <0x00 0xff>;
>> + num-lanes = <2>;
>> + #address-cells = <3>;
>> + #size-cells = <2>;
>> +
>> + ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x00100000>,
>> + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x0fd00000>;
>> + interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-names = "msi0",
>> + "msi1",
>> + "msi2",
>> + "msi3",
>> + "msi4",
>> + "msi5",
>> + "msi6",
>> + "msi7";
>
> Define the 'global' interrupt if it exists in hw.
>
>> +
>> + #interrupt-cells = <1>;
>> + interrupt-map-mask = <0 0 0 0x7>;
>> + interrupt-map = <0 0 0 1 &intc 0 479 IRQ_TYPE_LEVEL_HIGH>,
>> + <0 0 0 2 &intc 0 480 IRQ_TYPE_LEVEL_HIGH>,
>> + <0 0 0 3 &intc 0 481 IRQ_TYPE_LEVEL_HIGH>,
>> + <0 0 0 4 &intc 0 482 IRQ_TYPE_LEVEL_HIGH>;
>> +
>> + clocks = <&gcc GCC_PCIE3_AXI_M_CLK>,
>> + <&gcc GCC_PCIE3_AXI_S_CLK>,
>> + <&gcc GCC_PCIE3_AXI_S_BRIDGE_CLK>,
>> + <&gcc GCC_PCIE3_RCHNG_CLK>,
>> + <&gcc GCC_PCIE3_AHB_CLK>,
>> + <&gcc GCC_PCIE3_AUX_CLK>;
>> + clock-names = "axi_m",
>> + "axi_s",
>> + "axi_bridge",
>> + "rchng",
>> + "ahb",
>> + "aux";
>> +
>> + assigned-clocks = <&gcc GCC_PCIE3_AHB_CLK>,
>> + <&gcc GCC_PCIE3_AUX_CLK>,
>> + <&gcc GCC_PCIE3_AXI_M_CLK>,
>> + <&gcc GCC_PCIE3_AXI_S_BRIDGE_CLK>,
>> + <&gcc GCC_PCIE3_AXI_S_CLK>,
>> + <&gcc GCC_PCIE3_RCHNG_CLK>;
>> + assigned-clock-rates = <100000000>,
>> + <20000000>,
>> + <266666666>,
>> + <240000000>,
>> + <240000000>,
>> + <100000000>;
>
> Why does this platform has to assign clock rate for all the clocks?
>
Only the RCHNG clock requires rate configuration.
The other clocks have already been set according to the frequency plan.
Therefore, I will exclude all clocks except the RCHNG clock.
>> +
>> + resets = <&gcc GCC_PCIE3_PIPE_ARES>,
>> + <&gcc GCC_PCIE3_CORE_STICKY_RESET>,
>> + <&gcc GCC_PCIE3_AXI_S_STICKY_RESET>,
>> + <&gcc GCC_PCIE3_AXI_S_ARES>,
>> + <&gcc GCC_PCIE3_AXI_M_STICKY_RESET>,
>> + <&gcc GCC_PCIE3_AXI_M_ARES>,
>> + <&gcc GCC_PCIE3_AUX_ARES>,
>> + <&gcc GCC_PCIE3_AHB_ARES>;
>> + reset-names = "pipe",
>> + "sticky",
>> + "axi_s_sticky",
>> + "axi_s",
>> + "axi_m_sticky",
>> + "axi_m",
>> + "aux",
>> + "ahb";
>> +
>> + msi-map = <0x0 &intc 0x0 0x1000>;
>> +
>> + phys = <&pcie3_phy>;
>> + phy-names = "pciephy";
>> + interconnects = <&gcc MASTER_ANOC_PCIE3 &gcc SLAVE_ANOC_PCIE3>,
>> + <&gcc MASTER_CNOC_PCIE3 &gcc SLAVE_CNOC_PCIE3>;
>
> Define icc tags also.
>
Okay, sure.
Thanks & Regards,
Manikanta.
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