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Message-ID: <20250123170508.13578-9-john.madieu.xa@bp.renesas.com>
Date: Thu, 23 Jan 2025 18:05:07 +0100
From: John Madieu <john.madieu.xa@...renesas.com>
To: john.madieu.xa@...renesas.com,
geert+renesas@...der.be,
krzk+dt@...nel.org,
robh@...nel.org
Cc: biju.das.jz@...renesas.com,
claudiu.beznea.uj@...renesas.com,
conor+dt@...nel.org,
devicetree@...r.kernel.org,
john.madieu@...il.com,
linux-kernel@...r.kernel.org,
linux-renesas-soc@...r.kernel.org,
magnus.damm@...il.com
Subject: [PATCH v4 8/9] arm64: dts: renesas: r9a09g047: Add sys node
Add system controller node to RZ/G3E (R9A09G047) SoC DTSI, as it is also
required for SoC identification
Signed-off-by: John Madieu <john.madieu.xa@...renesas.com>
---
Changes:
v1 -> v2: No changes
v2 -> v3: No changes
v3 -> v4: No changes
arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
index 444fadaf7254..0840450dda47 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
@@ -162,6 +162,13 @@ cpg: clock-controller@...20000 {
#power-domain-cells = <0>;
};
+ sys: system-controller@...30000 {
+ compatible = "renesas,r9a09g047-sys";
+ reg = <0 0x10430000 0 0x10000>;
+ clocks = <&cpg CPG_CORE R9A09G047_SYS_0_PCLK>;
+ resets = <&cpg 0x30>;
+ };
+
ostm0: timer@...00000 {
compatible = "renesas,r9a09g047-ostm", "renesas,ostm";
reg = <0x0 0x11800000 0x0 0x1000>;
--
2.25.1
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