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Message-ID: <20250124061237.he34clwukqwzqx2t@thinkpad>
Date: Fri, 24 Jan 2025 11:42:37 +0530
From: Manivannan Sadhasivam <mani@...nel.org>
To: Krishna Chaitanya Chundru <krishna.chundru@....qualcomm.com>
Cc: cros-qcom-dts-watchers@...omium.org,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Lorenzo Pieralisi <lpieralisi@...nel.org>,
Krzysztof Wilczyński <kw@...ux.com>,
Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>,
Bjorn Helgaas <bhelgaas@...gle.com>,
Jingoo Han <jingoohan1@...il.com>, linux-arm-msm@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-pci@...r.kernel.org, quic_vbadigan@...cinc.com,
quic_vpernami@...cinc.com, quic_mrana@...cinc.com,
mmareddy@...cinc.com,
Krishna chaitanya chundru <quic_krichai@...cinc.com>
Subject: Re: [PATCH v3 2/4] PCI: dwc: Add ECAM support with iATU configuration
On Tue, Jan 21, 2025 at 02:32:20PM +0530, Krishna Chaitanya Chundru wrote:
> The current implementation requires iATU for every configuration
> space access which increases latency & cpu utilization.
>
> Designware databook 5.20a, section 3.10.10.3 says about CFG Shift Feature,
> which shifts/maps the BDF (bits [31:16] of the third header DWORD, which
> would be matched against the Base and Limit addresses) of the incoming
> CfgRd0/CfgWr0 down to bits[27:12]of the translated address.
>
> Configuring iATU in config shift feature enables ECAM feature to access the
> config space, which avoids iATU configuration for every config access.
>
> Add "ctrl2" into struct dw_pcie_ob_atu_cfg to enable config shift feature.
>
> As DBI comes under config space, this avoids remapping of DBI space
> separately. Instead, it uses the mapped config space address returned from
> ECAM initialization. Change the order of dw_pcie_get_resources() execution
> to achieve this.
>
> Enable the ECAM feature if the config space size is equal to size required
> to represent number of buses in the bus range property, add a function
> which checks this. The DWC glue drivers uses this function and decide to
> enable ECAM mode or not.
>
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@....qualcomm.com>
Some minor comments inline. Overall, the patch LGTM!
> ---
> drivers/pci/controller/dwc/Kconfig | 1 +
> drivers/pci/controller/dwc/pcie-designware-host.c | 139 +++++++++++++++++++---
> drivers/pci/controller/dwc/pcie-designware.c | 2 +-
> drivers/pci/controller/dwc/pcie-designware.h | 11 ++
> 4 files changed, 133 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
> index b6d6778b0698..73c3aed6b60a 100644
> --- a/drivers/pci/controller/dwc/Kconfig
> +++ b/drivers/pci/controller/dwc/Kconfig
> @@ -9,6 +9,7 @@ config PCIE_DW
> config PCIE_DW_HOST
> bool
> select PCIE_DW
> + select PCI_HOST_COMMON
>
> config PCIE_DW_EP
> bool
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index d2291c3ceb8b..3888f9fe5af1 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -418,6 +418,66 @@ static void dw_pcie_host_request_msg_tlp_res(struct dw_pcie_rp *pp)
> }
> }
>
> +static int dw_pcie_config_ecam_iatu(struct dw_pcie_rp *pp)
> +{
> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> + struct dw_pcie_ob_atu_cfg atu = {0};
> + resource_size_t bus_range_max;
> + struct resource_entry *bus;
> + int ret;
> +
> + bus = resource_list_first_type(&pp->bridge->windows, IORESOURCE_BUS);
> +
> + /*
> + * Root bus under the root port doesn't require any iATU configuration
You mean 'Root bus under host bridge'?
> + * as DBI space will represent Root bus configuration space.
> + * Immediate bus under Root Bus, needs type 0 iATU configuration and
> + * remaining buses need type 1 iATU configuration.
> + */
> + atu.index = 0;
> + atu.type = PCIE_ATU_TYPE_CFG0;
> + atu.cpu_addr = pp->cfg0_base + SZ_1M;
> + atu.size = SZ_1M;
> + atu.ctrl2 = PCIE_ATU_CFG_SHIFT_MODE_ENABLE;
> + ret = dw_pcie_prog_outbound_atu(pci, &atu);
> + if (ret)
> + return ret;
> +
> + bus_range_max = resource_size(bus->res);
> +
> + if (bus_range_max < 2)
> + return 0;
> +
> + /* Configure remaining buses in type 1 iATU configuration */
> + atu.index = 1;
> + atu.type = PCIE_ATU_TYPE_CFG1;
> + atu.cpu_addr = pp->cfg0_base + SZ_2M;
> + atu.size = (SZ_1M * (bus_range_max - 2));
> + atu.ctrl2 = PCIE_ATU_CFG_SHIFT_MODE_ENABLE;
> +
> + return dw_pcie_prog_outbound_atu(pci, &atu);
> +}
> +
> +static int dw_pcie_create_ecam_window(struct dw_pcie_rp *pp, struct resource *res)
> +{
> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> + struct device *dev = pci->dev;
> + struct resource_entry *bus;
> +
> + bus = resource_list_first_type(&pp->bridge->windows, IORESOURCE_BUS);
> + if (!bus)
> + return -ENODEV;
> +
> + pp->cfg = pci_ecam_create(dev, res, bus->res, &pci_generic_ecam_ops);
> + if (IS_ERR(pp->cfg))
> + return PTR_ERR(pp->cfg);
> +
> + pci->dbi_base = pp->cfg->win;
> + pci->dbi_phys_addr = res->start;
> +
> + return 0;
> +}
> +
> int dw_pcie_host_init(struct dw_pcie_rp *pp)
> {
> struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> @@ -431,19 +491,8 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp)
>
> raw_spin_lock_init(&pp->lock);
>
> - ret = dw_pcie_get_resources(pci);
> - if (ret)
> - return ret;
> -
> res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
> - if (res) {
> - pp->cfg0_size = resource_size(res);
> - pp->cfg0_base = res->start;
> -
> - pp->va_cfg0_base = devm_pci_remap_cfg_resource(dev, res);
> - if (IS_ERR(pp->va_cfg0_base))
> - return PTR_ERR(pp->va_cfg0_base);
> - } else {
> + if (!res) {
> dev_err(dev, "Missing *config* reg space\n");
> return -ENODEV;
> }
> @@ -454,6 +503,31 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp)
>
> pp->bridge = bridge;
>
> + pp->cfg0_size = resource_size(res);
> + pp->cfg0_base = res->start;
> +
> + if (pp->ecam_mode) {
> + ret = dw_pcie_create_ecam_window(pp, res);
> + if (ret)
> + return ret;
Add a newline here.
> + bridge->ops = (struct pci_ops *)&pci_generic_ecam_ops.pci_ops;
> + pp->bridge->sysdata = pp->cfg;
> + pp->cfg->priv = pp;
> + } else {
> + pp->va_cfg0_base = devm_pci_remap_cfg_resource(dev, res);
> + if (IS_ERR(pp->va_cfg0_base))
> + return PTR_ERR(pp->va_cfg0_base);
> +
> + /* Set default bus ops */
> + bridge->ops = &dw_pcie_ops;
> + bridge->child_ops = &dw_child_pcie_ops;
> + bridge->sysdata = pp;
> + }
> +
> + ret = dw_pcie_get_resources(pci);
> + if (ret)
> + goto err_free_ecam;
> +
> /* Get the I/O range from DT */
> win = resource_list_first_type(&bridge->windows, IORESOURCE_IO);
> if (win) {
> @@ -462,14 +536,10 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp)
> pp->io_base = pci_pio_to_address(win->res->start);
> }
>
> - /* Set default bus ops */
> - bridge->ops = &dw_pcie_ops;
> - bridge->child_ops = &dw_child_pcie_ops;
> -
> if (pp->ops->init) {
> ret = pp->ops->init(pp);
> if (ret)
> - return ret;
> + goto err_free_ecam;
> }
>
> if (pci_msi_enabled()) {
> @@ -504,6 +574,12 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp)
>
> dw_pcie_iatu_detect(pci);
>
> + if (pp->ecam_mode) {
> + ret = dw_pcie_config_ecam_iatu(pp);
> + if (ret)
Add a error print so that users will know what is going wrong.
> + goto err_free_msi;
> + }
> +
> /*
> * Allocate the resource for MSG TLP before programming the iATU
> * outbound window in dw_pcie_setup_rc(). Since the allocation depends
> @@ -533,8 +609,6 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp)
> /* Ignore errors, the link may come up later */
> dw_pcie_wait_for_link(pci);
>
> - bridge->sysdata = pp;
> -
> ret = pci_host_probe(bridge);
> if (ret)
> goto err_stop_link;
> @@ -558,6 +632,10 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp)
> if (pp->ops->deinit)
> pp->ops->deinit(pp);
>
> +err_free_ecam:
> + if (pp->cfg)
> + pci_ecam_free(pp->cfg);
> +
> return ret;
> }
> EXPORT_SYMBOL_GPL(dw_pcie_host_init);
> @@ -578,6 +656,9 @@ void dw_pcie_host_deinit(struct dw_pcie_rp *pp)
>
> if (pp->ops->deinit)
> pp->ops->deinit(pp);
> +
> + if (pp->cfg)
> + pci_ecam_free(pp->cfg);
> }
> EXPORT_SYMBOL_GPL(dw_pcie_host_deinit);
>
> @@ -985,3 +1066,23 @@ int dw_pcie_resume_noirq(struct dw_pcie *pci)
> return ret;
> }
> EXPORT_SYMBOL_GPL(dw_pcie_resume_noirq);
> +
> +bool dw_pcie_ecam_supported(struct dw_pcie_rp *pp)
> +{
> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> + struct platform_device *pdev = to_platform_device(pci->dev);
> + struct resource *config_res, *bus_range;
> + u64 bus_config_space_count;
> +
> + bus_range = resource_list_first_type(&pp->bridge->windows, IORESOURCE_BUS)->res;
> + if (!bus_range)
> + return false;
> +
> + config_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
> + if (!config_res)
> + return false;
> +
> + bus_config_space_count = resource_size(config_res) >> PCIE_ECAM_BUS_SHIFT;
> +
> + return bus_config_space_count >= resource_size(bus_range);
return !!(bus_config_space_count >= resource_size(bus_range));
You should export this API also to avoid someone sending a fix patch later if
this gets called from a modular driver.
- Mani
--
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