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Message-Id: <20250124064619.13893-3-zhangqing@rock-chips.com> Date: Fri, 24 Jan 2025 14:46:18 +0800 From: Elaine Zhang <zhangqing@...k-chips.com> To: mturquette@...libre.com, sboyd@...nel.org, kever.yang@...k-chips.com, zhangqing@...k-chips.com, heiko@...ech.de, robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org Cc: linux-clk@...r.kernel.org, linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org, huangtao@...k-chips.com, devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org Subject: [PATCH v1 2/3] Revert "arm64: dts: rockchip: Increase VOP clk rate on RK3328" This reverts commit 0f2ddb128fa20f8441d903285632f2c69e90fae1. Before changing the PLL frequency, in order to avoid overclocking the child clock, set the child clock to a large div first, and then set the CLK as required after the PLL is set. Signed-off-by: Elaine Zhang <zhangqing@...k-chips.com> --- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index 7d992c3c01ce..f3ef8cbfbdae 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -852,8 +852,8 @@ <0>, <24000000>, <24000000>, <24000000>, <15000000>, <15000000>, - <300000000>, <100000000>, - <400000000>, <100000000>, + <100000000>, <100000000>, + <100000000>, <100000000>, <50000000>, <100000000>, <100000000>, <100000000>, <50000000>, <50000000>, -- 2.17.1
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