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Message-ID: <f2c9061a-6a9c-4cd1-8a3f-a286a2eb30a8@linux.intel.com>
Date: Fri, 24 Jan 2025 16:10:41 +0200 (EET)
From: Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>
To: Matthew Gerlach <matthew.gerlach@...ux.intel.com>
cc: lpieralisi@...nel.org, kw@...ux.com, manivannan.sadhasivam@...aro.org,
robh@...nel.org, bhelgaas@...gle.com, krzk+dt@...nel.org,
conor+dt@...nel.org, dinguyen@...nel.org, joyce.ooi@...el.com,
linux-pci@...r.kernel.org, devicetree@...r.kernel.org,
LKML <linux-kernel@...r.kernel.org>, matthew.gerlach@...era.com,
peter.colberg@...era.com,
"D M, Sharath Kumar" <sharath.kumar.d.m@...el.com>, D@....codeaurora.org,
M@....codeaurora.org
Subject: Re: [PATCH v4 5/5] PCI: altera: Add Agilex support
On Thu, 23 Jan 2025, Matthew Gerlach wrote:
> From: "D M, Sharath Kumar" <sharath.kumar.d.m@...el.com>
>
> Add PCIe root port controller support for the Agilex family of chips.
> The Agilex PCIe IP has three variants that are mostly sw compatible,
> except for a couple register offsets. The P-Tile variant supports
> Gen3/Gen4 1x16. The F-Tile variant supports Gen3/Gen4 4x4, 4x8, and 4x16.
> The R-Tile variant improves on the F-Tile variant by adding Gen5 support.
>
> To simplify the implementation of pci_ops read/write functions,
> ep_{read/write}_cfg() callbacks were added to struct altera_pci_ops
> to easily distinguish between hardware variants.
>
> Signed-off-by: D M, Sharath Kumar <sharath.kumar.d.m@...el.com>
> Signed-off-by: Matthew Gerlach <matthew.gerlach@...ux.intel.com>
> ---
> v4:
> - Add info to commit message.
> - Use {read/write}?_relaxed where appropriate.
> - Use BIT(12) instead of (1 << 12).
> - Clear IRQ before handling it.
> - add interrupt number to unexpected IRQ messge.
>
> v3:
> - Remove accepted patches from patch set.
>
> v2:
> - Match historical style of subject.
> - Remove unrelated changes.
> - Fix indentation.
> ---
> drivers/pci/controller/pcie-altera.c | 246 ++++++++++++++++++++++++++-
> 1 file changed, 237 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/pci/controller/pcie-altera.c b/drivers/pci/controller/pcie-altera.c
> index eb55a7f8573a..59cad9a84900 100644
> --- a/drivers/pci/controller/pcie-altera.c
> +++ b/drivers/pci/controller/pcie-altera.c
> @@ -77,9 +77,19 @@
> #define S10_TLP_FMTTYPE_CFGWR0 0x45
> #define S10_TLP_FMTTYPE_CFGWR1 0x44
>
> +#define AGLX_RP_CFG_ADDR(pcie, reg) (((pcie)->hip_base) + (reg))
> +#define AGLX_RP_SECONDARY(pcie) \
> + readb(AGLX_RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
> +
> +#define AGLX_BDF_REG 0x00002004
> +#define AGLX_ROOT_PORT_IRQ_STATUS 0x14c
> +#define AGLX_ROOT_PORT_IRQ_ENABLE 0x150
> +#define CFG_AER BIT(4)
> +
> enum altera_pcie_version {
> ALTERA_PCIE_V1 = 0,
> ALTERA_PCIE_V2,
> + ALTERA_PCIE_V3,
> };
>
> struct altera_pcie {
> @@ -102,6 +112,11 @@ struct altera_pcie_ops {
> int size, u32 *value);
> int (*rp_write_cfg)(struct altera_pcie *pcie, u8 busno,
> int where, int size, u32 value);
> + int (*ep_read_cfg)(struct altera_pcie *pcie, u8 busno,
> + unsigned int devfn, int where, int size, u32 *value);
> + int (*ep_write_cfg)(struct altera_pcie *pcie, u8 busno,
> + unsigned int devfn, int where, int size, u32 value);
> + void (*rp_isr)(struct irq_desc *desc);
> };
>
> struct altera_pcie_data {
> @@ -112,6 +127,9 @@ struct altera_pcie_data {
> u32 cfgrd1;
> u32 cfgwr0;
> u32 cfgwr1;
> + u32 port_conf_offset;
> + u32 port_irq_status_offset;
> + u32 port_irq_enable_offset;
> };
>
> struct tlp_rp_regpair_t {
> @@ -131,6 +149,28 @@ static inline u32 cra_readl(struct altera_pcie *pcie, const u32 reg)
> return readl_relaxed(pcie->cra_base + reg);
> }
>
> +static inline void cra_writew(struct altera_pcie *pcie, const u32 value,
> + const u32 reg)
> +{
> + writew_relaxed(value, pcie->cra_base + reg);
> +}
> +
> +static inline u32 cra_readw(struct altera_pcie *pcie, const u32 reg)
> +{
> + return readw_relaxed(pcie->cra_base + reg);
> +}
> +
> +static inline void cra_writeb(struct altera_pcie *pcie, const u32 value,
> + const u32 reg)
> +{
> + writeb_relaxed(value, pcie->cra_base + reg);
> +}
> +
> +static inline u32 cra_readb(struct altera_pcie *pcie, const u32 reg)
> +{
> + return readb_relaxed(pcie->cra_base + reg);
> +}
> +
> static bool altera_pcie_link_up(struct altera_pcie *pcie)
> {
> return !!((cra_readl(pcie, RP_LTSSM) & RP_LTSSM_MASK) == LTSSM_L0);
> @@ -145,6 +185,15 @@ static bool s10_altera_pcie_link_up(struct altera_pcie *pcie)
> return !!(readw(addr) & PCI_EXP_LNKSTA_DLLLA);
> }
>
> +static bool aglx_altera_pcie_link_up(struct altera_pcie *pcie)
> +{
> + void __iomem *addr = AGLX_RP_CFG_ADDR(pcie,
> + pcie->pcie_data->cap_offset +
> + PCI_EXP_LNKSTA);
> +
> + return !!(readw_relaxed(addr) & PCI_EXP_LNKSTA_DLLLA);
This returns bool so double negations are not necessary.
> +}
> +
> /*
> * Altera PCIe port uses BAR0 of RC's configuration space as the translation
> * from PCI bus to native BUS. Entire DDR region is mapped into PCIe space
> @@ -425,6 +474,103 @@ static int s10_rp_write_cfg(struct altera_pcie *pcie, u8 busno,
> return PCIBIOS_SUCCESSFUL;
> }
>
> +static int aglx_rp_read_cfg(struct altera_pcie *pcie, int where,
> + int size, u32 *value)
> +{
> + void __iomem *addr = AGLX_RP_CFG_ADDR(pcie, where);
> +
> + switch (size) {
> + case 1:
> + *value = readb_relaxed(addr);
> + break;
> + case 2:
> + *value = readw_relaxed(addr);
> + break;
> + default:
> + *value = readl_relaxed(addr);
> + break;
> + }
> +
> + /* interrupt pin not programmed in hardware, set to INTA */
> + if (where == PCI_INTERRUPT_PIN && size == 1 && !(*value))
> + *value = 0x01;
> + else if (where == PCI_INTERRUPT_LINE && !(*value & 0xff00))
> + *value |= 0x0100;
> +
> + return PCIBIOS_SUCCESSFUL;
> +}
> +
> +static int aglx_rp_write_cfg(struct altera_pcie *pcie, u8 busno,
> + int where, int size, u32 value)
> +{
> + void __iomem *addr = AGLX_RP_CFG_ADDR(pcie, where);
> +
> + switch (size) {
> + case 1:
> + writeb_relaxed(value, addr);
> + break;
> + case 2:
> + writew_relaxed(value, addr);
> + break;
> + default:
> + writel_relaxed(value, addr);
> + break;
> + }
> +
> + /*
> + * Monitor changes to PCI_PRIMARY_BUS register on root port
> + * and update local copy of root bus number accordingly.
> + */
> + if (busno == pcie->root_bus_nr && where == PCI_PRIMARY_BUS)
> + pcie->root_bus_nr = value & 0xff;
> +
> + return PCIBIOS_SUCCESSFUL;
> +}
> +
> +static int aglx_ep_write_cfg(struct altera_pcie *pcie, u8 busno,
> + unsigned int devfn, int where, int size, u32 value)
> +{
> + cra_writel(pcie, ((busno << 8) | devfn), AGLX_BDF_REG);
> + if (busno > AGLX_RP_SECONDARY(pcie))
> + where |= BIT(12); /* type 1 */
Add a define to replace the comment?
> +
> + switch (size) {
> + case 1:
> + cra_writeb(pcie, value, where);
> + break;
> + case 2:
> + cra_writew(pcie, value, where);
> + break;
> + default:
> + cra_writel(pcie, value, where);
> + break;
> + }
> +
> + return PCIBIOS_SUCCESSFUL;
> +}
> +
> +static int aglx_ep_read_cfg(struct altera_pcie *pcie, u8 busno,
> + unsigned int devfn, int where, int size, u32 *value)
> +{
> + cra_writel(pcie, ((busno << 8) | devfn), AGLX_BDF_REG);
> + if (busno > AGLX_RP_SECONDARY(pcie))
> + where |= BIT(12); /* type 1 */
Same here?
--
i.
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