linux-kernel - Re: [PATCH v4 4/9] soc: renesas: rz-sysc: Add support for RZ/G3E family

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Message-ID: <CAMuHMdWHuwdYfm_b9uO8LjmJpAwyRrBTJbeoz5FOyEcYSJqL9A@mail.gmail.com>
Date: Fri, 24 Jan 2025 15:20:26 +0100
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: John Madieu <john.madieu.xa@...renesas.com>
Cc: geert+renesas@...der.be, krzk+dt@...nel.org, robh@...nel.org, 
	biju.das.jz@...renesas.com, claudiu.beznea.uj@...renesas.com, 
	conor+dt@...nel.org, devicetree@...r.kernel.org, john.madieu@...il.com, 
	linux-kernel@...r.kernel.org, linux-renesas-soc@...r.kernel.org, 
	magnus.damm@...il.com
Subject: Re: [PATCH v4 4/9] soc: renesas: rz-sysc: Add support for RZ/G3E family

Hi John,

On Thu, Jan 23, 2025 at 6:05 PM John Madieu
<john.madieu.xa@...renesas.com> wrote:
> Add SoC detection support for RZ/G3E SoC. Also add support for detecting
> the number of cores and ETHOS-U55 NPU and also detect PLL mismatch for SW
> settings other than 1.7GHz.
>
> Signed-off-by: John Madieu <john.madieu.xa@...renesas.com>
> ---
> v3 -> v4: No changes
>
> Changes in v3:
> - Removed Syscon support
>
> Changes in v2:
> - Group bitfields ordered by registers
> - Rename SoC-specific callback field to 'print_id'
> - Explicitely select 'MFD_SYSCON' config option
> - Do not rely on 'syscon'-compatible probing anymore.

Thanks for the update!

> --- /dev/null
> +++ b/drivers/soc/renesas/r9a09g047-sys.c
> @@ -0,0 +1,71 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * RZ/G3E System controller (SYS) driver
> + *
> + * Copyright (C) 2025 Renesas Electronics Corp.
> + */
> +
> +#include <linux/bits.h>
> +#include <linux/device.h>
> +#include <linux/init.h>
> +#include <linux/io.h>
> +
> +#include "rz-sysc.h"
> +
> +/* Register Offsets */
> +#define SYS_LSI_MODE           0x300
> +/*
> + * BOOTPLLCA[1:0]
> + *         [0,0] => 1.1GHZ
> + *         [0,1] => 1.5GHZ
> + *         [1,0] => 1.6GHZ
> + *         [1,1] => 1.7GHZ
> + */
> +#define SYS_LSI_MODE_STAT_BOOTPLLCA55  GENMASK(12, 11)
> +#define SYS_LSI_MODE_CA55_1_7GHZ       0x3

Please add a blank line here.

> +#define SYS_LSI_DEVID          0x304
> +#define SYS_LSI_DEVID_REV      GENMASK(31, 28)
> +#define SYS_LSI_DEVID_SPECIFIC GENMASK(27, 0)

Please align the second column in the three lines above.
Please add a blank line here.

> +#define SYS_LSI_PRR                    0x308
> +#define SYS_LSI_PRR_CA55_DIS           BIT(8)
> +#define SYS_LSI_PRR_NPU_DIS            BIT(1)
> +
> +
> +static void rzg3e_sys_print_id(struct device *dev,
> +                               void __iomem *sysc_base,
> +                               struct soc_device_attribute *soc_dev_attr)
> +{
> +       bool is_quad_core, npu_enabled;
> +       u32 prr_val, mode_val;
> +
> +       prr_val = readl(sysc_base + SYS_LSI_PRR);
> +       mode_val = readl(sysc_base + SYS_LSI_MODE);
> +
> +       /* Check CPU and NPU configuration */
> +       is_quad_core = !(prr_val & SYS_LSI_PRR_CA55_DIS);
> +       npu_enabled = !(prr_val & SYS_LSI_PRR_NPU_DIS);
> +
> +       dev_info(dev, "Detected Renesas %s Core %s %s Rev %s%s\n",
> +                is_quad_core ? "Quad" : "Dual",
> +                soc_dev_attr->family,

Fits on a single line.

> +                soc_dev_attr->soc_id,
> +                soc_dev_attr->revision,

Likewise.

> +                npu_enabled ? " with Ethos-U55" : "");
> +
> +       /* Check CA55 PLL configuration */
> +       if (FIELD_GET(SYS_LSI_MODE_STAT_BOOTPLLCA55, mode_val) != SYS_LSI_MODE_CA55_1_7GHZ)
> +               dev_warn(dev, "CA55 PLL is not set to 1.7GHz\n");
> +}

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds