linux-kernel - Re: [PATCH v1 1/3] Revert "clk: rockchip: Set parent rate for DCLK

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Message-ID: <d95d317c-5f6e-42bd-94a9-e1a6c7685e2f@kwiboo.se>
Date: Fri, 24 Jan 2025 15:40:56 +0100
From: Jonas Karlman <jonas@...boo.se>
To: Elaine Zhang <zhangqing@...k-chips.com>
Cc: mturquette@...libre.com, sboyd@...nel.org, kever.yang@...k-chips.com,
 heiko@...ech.de, robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
 linux-clk@...r.kernel.org, linux-rockchip@...ts.infradead.org,
 linux-kernel@...r.kernel.org, huangtao@...k-chips.com,
 devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v1 1/3] Revert "clk: rockchip: Set parent rate for
 DCLK_VOP clock on RK3228"

Hi Elaine,

On 2025-01-24 07:46, Elaine Zhang wrote:
> This reverts commit 1d34b9757523c1ad547bd6d040381f62d74a3189.
> 
> RK3228 Only GPLL and CPLL, GPLL is a common clock, does not allow
> dclk_vop to change its frequency, CPLL is used by GMAC,
> if dclk_vop use CLK_SET_RATE_PARENT and CLK_SET_RATE_NO_REPARENT flags will
> affect the GMAC function.

Please explain how CPLL and GPLL is affected by this? According to TRM
the hdmiphy is default parent (reset value), this is also how similar
clock is defined for RK3328.

  vop_pll_sel  
  Control vop clock PLL source selection.  
  1'b0: select hdmiphy pll clock (reset value)
  1'b1: select vop dclk

Maybe the dclk_vop name is causing confusion, or am I missing something?

Regards,
Jonas

> 
> If the client application does not use GMAC and CPLL is free, make this
> change on the local branch.
> 
> Signed-off-by: Elaine Zhang <zhangqing@...k-chips.com>
> ---
>  drivers/clk/rockchip/clk-rk3228.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
> index ed602c27b624..9c0284607766 100644
> --- a/drivers/clk/rockchip/clk-rk3228.c
> +++ b/drivers/clk/rockchip/clk-rk3228.c
> @@ -409,7 +409,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
>  			RK2928_CLKSEL_CON(29), 0, 3, DFLAGS),
>  	DIV(0, "sclk_vop_pre", "sclk_vop_src", 0,
>  			RK2928_CLKSEL_CON(27), 8, 8, DFLAGS),
> -	MUX(DCLK_VOP, "dclk_vop", mux_dclk_vop_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
> +	MUX(DCLK_VOP, "dclk_vop", mux_dclk_vop_p, 0,
>  			RK2928_CLKSEL_CON(27), 1, 1, MFLAGS),
>  
>  	FACTOR(0, "xin12m", "xin24m", 0, 1, 2),