| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <243e80e7-7987-411f-9c60-171897113853@foss.st.com>
Date: Fri, 24 Jan 2025 16:42:01 +0100
From: Christian Bruel <christian.bruel@...s.st.com>
To: Rob Herring <robh@...nel.org>
CC: <bhelgaas@...gle.com>, <lpieralisi@...nel.org>, <kw@...ux.com>,
<manivannan.sadhasivam@...aro.org>, <krzk+dt@...nel.org>,
<conor+dt@...nel.org>, <mcoquelin.stm32@...il.com>,
<alexandre.torgue@...s.st.com>, <jingoohan1@...il.com>,
<p.zabel@...gutronix.de>, <johan+linaro@...nel.org>,
<quic_schintav@...cinc.com>, <cassel@...nel.org>,
<linux-pci@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-stm32@...md-mailman.stormreply.com>,
<linux-arm-kernel@...ts.infradead.org>, <linux-kernel@...r.kernel.org>,
<fabrice.gasnier@...s.st.com>
Subject: Re: [PATCH v3 01/10] dt-bindings: PCI: Add STM32MP25 PCIe Root
Complex bindings
On 1/23/25 22:38, Rob Herring wrote:
> On Wed, Jan 15, 2025 at 10:21:25AM +0100, Christian Bruel wrote:
>> Document the bindings for STM32MP25 PCIe Controller configured in
>> root complex mode.
>>
>> Supports 4 INTx and MSI interrupts from the ARM GICv2m controller.
>>
>> STM32 PCIe may be in a power domain which is the case for the STM32MP25
>> based boards.
>>
>> Supports WAKE# from wake-gpios
>>
>> Signed-off-by: Christian Bruel <christian.bruel@...s.st.com>
>> ---
>> .../bindings/pci/st,stm32-pcie-common.yaml | 43 +++++++
>> .../bindings/pci/st,stm32-pcie-host.yaml | 120 ++++++++++++++++++
>> 2 files changed, 163 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/pci/st,stm32-pcie-common.yaml
>> create mode 100644 Documentation/devicetree/bindings/pci/st,stm32-pcie-host.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/pci/st,stm32-pcie-common.yaml b/Documentation/devicetree/bindings/pci/st,stm32-pcie-common.yaml
>> new file mode 100644
>> index 000000000000..9ee25bb25aac
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pci/st,stm32-pcie-common.yaml
>> @@ -0,0 +1,43 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/pci/st,stm32-pcie-common.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: STM32MP25 PCIe RC/EP controller
>> +
>> +maintainers:
>> + - Christian Bruel <christian.bruel@...s.st.com>
>> +
>> +description:
>> + STM32MP25 PCIe RC/EP common properties
>> +
>> +properties:
>> + clocks:
>> + maxItems: 1
>> + description: PCIe system clock
>> +
>> + resets:
>> + maxItems: 1
>> +
>> + phys:
>> + maxItems: 1
>
> You have phys in host bridge and the root ports?
my mistake, need to cleanup stm32-pcie-common now that the phy has moved
to the root port part for the host
>
>> +
>> + phy-names:
>> + const: pcie-phy
>
> -names is unless when there is only 1 entry. We already know it's a
> 'phy' for 'pcie', so the whole string adds nothing.
OK
>
>> +
>> + power-domains:
>> + maxItems: 1
>> +
>> + access-controllers:
>> + maxItems: 1
>> +
>> + reset-gpios:
>> + description: GPIO controlled connection to PERST# signal
>> + maxItems: 1
>
> You have multiple root ports, but only one PERST# signal?
we have only one root port, but I agree, the signals (along with WAKE)
belong to the root port child
thanks,
Christian
>
>> +
>> +required:
>> + - clocks
>> + - resets
>> +
>> +additionalProperties: true
>> diff --git a/Documentation/devicetree/bindings/pci/st,stm32-pcie-host.yaml b/Documentation/devicetree/bindings/pci/st,stm32-pcie-host.yaml
>> new file mode 100644
>> index 000000000000..b5b8c92522e0
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pci/st,stm32-pcie-host.yaml
>> @@ -0,0 +1,120 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/pci/st,stm32-pcie-host.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: STMicroelectronics STM32MP25 PCIe Root Complex
>> +
>> +maintainers:
>> + - Christian Bruel <christian.bruel@...s.st.com>
>> +
>> +description:
>> + PCIe root complex controller based on the Synopsys DesignWare PCIe core.
>> +
>> +allOf:
>> + - $ref: /schemas/pci/snps,dw-pcie.yaml#
>> + - $ref: /schemas/pci/st,stm32-pcie-common.yaml#
>> +
>> +properties:
>> + compatible:
>> + const: st,stm32mp25-pcie-rc
>> +
>> + reg:
>> + items:
>> + - description: Data Bus Interface (DBI) registers.
>> + - description: PCIe configuration registers.
>> +
>> + reg-names:
>> + items:
>> + - const: dbi
>> + - const: config
>> +
>> + msi-parent:
>> + maxItems: 1
>> +
>> + wake-gpios:
>> + description: GPIO used as WAKE# input signal
>> + maxItems: 1
>> +
>> + wakeup-source: true
>> +
>> +dependentRequired:
>> + wakeup-source: [ wake-gpios ]
>> +
>> +patternProperties:
>> + '^pcie@[0-2],0$':
>> + type: object
>> + $ref: /schemas/pci/pci-pci-bridge.yaml#
>> +
>> + properties:
>> + reg:
>> + maxItems: 1
>> +
>> + phys:
>> + maxItems: 1
>> +
>> + phy-names:
>> + const: pcie-phy
>> +
>> + required:
>> + - phys
>> + - phy-names
>> + - ranges
>> +
>> + unevaluatedProperties: false
>> +
>> +required:
>> + - interrupt-map
>> + - interrupt-map-mask
>> + - ranges
>> + - dma-ranges
>> +
>> +unevaluatedProperties: false
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/clock/st,stm32mp25-rcc.h>
>> + #include <dt-bindings/gpio/gpio.h>
>> + #include <dt-bindings/interrupt-controller/arm-gic.h>
>> + #include <dt-bindings/phy/phy.h>
>> + #include <dt-bindings/reset/st,stm32mp25-rcc.h>
>> +
>> + pcie@...00000 {
>> + compatible = "st,stm32mp25-pcie-rc";
>> + device_type = "pci";
>> + reg = <0x48400000 0x400000>,
>> + <0x10000000 0x10000>;
>> + reg-names = "dbi", "config";
>> + #interrupt-cells = <1>;
>> + interrupt-map-mask = <0 0 0 7>;
>> + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
>> + <0 0 0 2 &intc 0 0 GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
>> + <0 0 0 3 &intc 0 0 GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
>> + <0 0 0 4 &intc 0 0 GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <3>;
>> + #size-cells = <2>;
>> + ranges = <0x01000000 0x0 0x00000000 0x10010000 0x0 0x10000>,
>> + <0x02000000 0x0 0x10020000 0x10020000 0x0 0x7fe0000>,
>> + <0x42000000 0x0 0x18000000 0x18000000 0x0 0x8000000>;
>> + dma-ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x80000000>;
>> + clocks = <&rcc CK_BUS_PCIE>;
>> + resets = <&rcc PCIE_R>;
>> + msi-parent = <&v2m0>;
>> + wakeup-source;
>> + wake-gpios = <&gpioh 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
>> + reset-gpios = <&gpioj 8 GPIO_ACTIVE_LOW>;
>> + access-controllers = <&rifsc 68>;
>> + power-domains = <&CLUSTER_PD>;
>> +
>> + pcie@0,0 {
>> + device_type = "pci";
>> + reg = <0x0 0x0 0x0 0x0 0x0>;
>> + phys = <&combophy PHY_TYPE_PCIE>;
>> + phy-names = "pcie-phy";
>> + #address-cells = <3>;
>> + #size-cells = <2>;
>> + ranges;
>> + };
>> +
>> + };
>> --
>> 2.34.1
>>
Powered by blists - more mailing lists