linux-kernel - Re: [PATCH V2 0/4] Add versal-pci driver

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Message-ID: <Z5YAEXtUWgB82JD3@yilunxu-OptiPlex-7050>
Date: Sun, 26 Jan 2025 17:27:45 +0800
From: Xu Yilun <yilun.xu@...ux.intel.com>
To: Yidong Zhang <yidong.zhang@....com>
Cc: linux-kernel@...r.kernel.org, linux-fpga@...r.kernel.org,
	mdf@...nel.org, hao.wu@...el.com, yilun.xu@...el.com,
	lizhi.hou@....com
Subject: Re: [PATCH V2 0/4] Add versal-pci driver

On Tue, Dec 10, 2024 at 10:37:29AM -0800, Yidong Zhang wrote:
> This patchset introduces a new Linux Kernel Driver, versal-pci for AMD
> Alevo Versal based PCIe Card. The driver is based on Linux fpga driver
> framework.
> 
> The AMD Alevo Versal based PCIe Card, including V70, is the first Alevo
> production card leveraging AMD XDNA architecture with AI Engines. It is
> designed for AI inference efficiency and is tuned for video analytics and
> natural language processing applications [1].
> 
> This versal-pci driver provides services, including:
>   - leveraging linux firmware and FPGA framework to download management
>     firmware
>   - program additional bit-streams for AMD Xilinx specific hardware
>   - communicate with PCIe user function
>   - communicate with firmware running on the PCIe Card
>   - monitor device health
> 
> The driver is licensed under GPL-2.0.
> 
> The firmware and bit-streams are distributed as a closed binary, delivered
> by AMD. Please see [1] for more information.
> 
> [1] https://www.amd.com/en/products/accelerators/alveo/v70.html
> 
> Refactor driver to address all comments from v1.
> Changes since v1:
> - Add driver architecture description.
> - Change the driver name to versal-pci 
> - Remove unnecessary memcpy in versal-pci-comm-chan.c
> - Keep mod_timer because we need single_threaded_queue with delayed_work.
> - Change the "comms" to "comm_chan".
> - Remove regmap, use base+offset directly.
> - Add skeleton ops with on implementation (TODO) for fpga_manager in early
>   patch (0001) and add implementation in later patch(0004).
> - Remove br_ops and FPGA region, no need.

I never said FPGA region is no need. FPGA region is the essential for
managing the reprogramming and re-enumeration.

Thanks,
Yilun