linux-kernel - Re: [External] Re: [PATCH RESEND] irqchip: riscv: Order normal writes and IPI writes

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Message-ID: <CAPYmKFtQVxYTurHox+ykLPL7MqsMyx8MFZabN1y5eO_EJzU02Q@mail.gmail.com>
Date: Mon, 27 Jan 2025 22:26:50 +0800
From: Xu Lu <luxu.kernel@...edance.com>
To: Thomas Gleixner <tglx@...utronix.de>
Cc: anup@...infault.org, charlie@...osinc.com, paul.walmsley@...ive.com, 
	palmer@...belt.com, lihangjing@...edance.com, xieyongji@...edance.com, 
	linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [External] Re: [PATCH RESEND] irqchip: riscv: Order normal writes
 and IPI writes

On Mon, Jan 27, 2025 at 6:33 PM Thomas Gleixner <tglx@...utronix.de> wrote:
>
> On Mon, Jan 27 2025 at 17:38, Xu Lu wrote:
>
> This is not a RESEND. The change log has been modified, no?

Sure, the change log has been modified. I will pay attention next time.

>
> The prefix is incorrect. See
>
>   https://www.kernel.org/doc/html/latest/process/maintainer-tip.html
>
> > RISC-V distinguishes between normal memory accesses and device I/O and
>
> What is a normal memory write? Are there abnormal memory writes too?

Sorry for the misleading. By normal memory write, I mean memory writes
and want to distinguish it from MMIO writes.

>
> > uses FENCE instruction to order them as viewed by othe RISC-V harts and
> > external devices or coprocessors. The FENCE instruction can order any
> > combination of device input(I), device output(O), memory reads(R) and
> > memory writes(W). For example, 'fence w, o' can be used to ensure all
>
> Can be? It _is_ used, no?

Yes, it _is_ used. 'Can be' is not accurate.

>
> > memory writes from instructions preceding the FENCE instruction appear
> > earlier in the global memory order than device output writes from
> > instructions after the FENCE instruction.
> >
> > RISC-V issues IPI by writing certain value to IMSIC/ACLINT MMIO
> > registers, which is regarded as device output operation. However, the
> > existing implementation of IMSIC/ACLINT driver issues IPI via
> > writel_relaxed(), which does not guarantee the order of device output
> > operation and preceding memory writes. Then the hart receiving IPI may
> > not have seen the latest data yet.
> >
> > This commit fixes this by replacing writel_relaxed() with writel()
> > when
>
> 'This commit' is equally wrong as 'This patch'. See Documentation/process/

Thanks very much. I will check the documents.

Best Regards,

Xu Lu

>
> > issuing IPI, which will use 'fence w, o' to ensure all previous writes
> > made by current hart are visible to other harts before they receive
> > the IPI.
>
> I've fixed it up for you.
>
> Thanks,
>
>         tglx