linux-kernel - Re: [PATCH 02/20] perf/x86/intel: Fix ARCH_PERFMON_NUM_COUNTER

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <6d5c45b4-53ad-403f-9de3-a25b80a44e0e@linux.intel.com>
Date: Mon, 27 Jan 2025 11:43:53 -0500
From: "Liang, Kan" <kan.liang@...ux.intel.com>
To: Peter Zijlstra <peterz@...radead.org>,
 Dapeng Mi <dapeng1.mi@...ux.intel.com>
Cc: Ingo Molnar <mingo@...hat.com>, Arnaldo Carvalho de Melo
 <acme@...nel.org>, Namhyung Kim <namhyung@...nel.org>,
 Ian Rogers <irogers@...gle.com>, Adrian Hunter <adrian.hunter@...el.com>,
 Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
 Andi Kleen <ak@...ux.intel.com>, Eranian Stephane <eranian@...gle.com>,
 linux-kernel@...r.kernel.org, linux-perf-users@...r.kernel.org,
 Dapeng Mi <dapeng1.mi@...el.com>, stable@...r.kernel.org
Subject: Re: [PATCH 02/20] perf/x86/intel: Fix ARCH_PERFMON_NUM_COUNTER_LEAF



On 2025-01-27 11:29 a.m., Peter Zijlstra wrote:
> On Thu, Jan 23, 2025 at 02:07:03PM +0000, Dapeng Mi wrote:
>> From: Kan Liang <kan.liang@...ux.intel.com>
>>
>> The EAX of the CPUID Leaf 023H enumerates the mask of valid sub-leaves.
>> To tell the availability of the sub-leaf 1 (enumerate the counter mask),
>> perf should check the bit 1 (0x2) of EAS, rather than bit 0 (0x1).
>>
>> The error is not user-visible on bare metal. Because the sub-leaf 0 and
>> the sub-leaf 1 are always available. However, it may bring issues in a
>> virtualization environment when a VMM only enumerates the sub-leaf 0.
>>
>> Fixes: eb467aaac21e ("perf/x86/intel: Support Architectural PerfMon Extension leaf")
>> Signed-off-by: Kan Liang <kan.liang@...ux.intel.com>
>> Cc: stable@...r.kernel.org
>> ---
>>  arch/x86/events/intel/core.c      | 4 ++--
>>  arch/x86/include/asm/perf_event.h | 2 +-
>>  2 files changed, 3 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
>> index 5e8521a54474..12eb96219740 100644
>> --- a/arch/x86/events/intel/core.c
>> +++ b/arch/x86/events/intel/core.c
>> @@ -4966,8 +4966,8 @@ static void update_pmu_cap(struct x86_hybrid_pmu *pmu)
>>  	if (ebx & ARCH_PERFMON_EXT_EQ)
>>  		pmu->config_mask |= ARCH_PERFMON_EVENTSEL_EQ;
>>  
>> -	if (sub_bitmaps & ARCH_PERFMON_NUM_COUNTER_LEAF_BIT) {
>> -		cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_NUM_COUNTER_LEAF,
>> +	if (sub_bitmaps & ARCH_PERFMON_NUM_COUNTER_LEAF) {
>> +		cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_NUM_COUNTER_LEAF_BIT,
>>  			    &eax, &ebx, &ecx, &edx);
>>  		pmu->cntr_mask64 = eax;
>>  		pmu->fixed_cntr_mask64 = ebx;
>> diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
>> index adaeb8ca3a8a..71e2ae021374 100644
>> --- a/arch/x86/include/asm/perf_event.h
>> +++ b/arch/x86/include/asm/perf_event.h
>> @@ -197,7 +197,7 @@ union cpuid10_edx {
>>  #define ARCH_PERFMON_EXT_UMASK2			0x1
>>  #define ARCH_PERFMON_EXT_EQ			0x2
>>  #define ARCH_PERFMON_NUM_COUNTER_LEAF_BIT	0x1
>> -#define ARCH_PERFMON_NUM_COUNTER_LEAF		0x1
>> +#define ARCH_PERFMON_NUM_COUNTER_LEAF		BIT(ARCH_PERFMON_NUM_COUNTER_LEAF_BIT)
> 
> if you'll look around, you'll note this file uses BIT_ULL(), please stay
> consistent.

But they are used for a 64-bit register.
The ARCH_PERFMON_NUM_COUNTER_LEAF is for the CPUID enumeration, which is
a u32.

Thanks,
Kan