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Message-Id: <7811b481-0227-42bb-a5ce-1d9794f5a196@app.fastmail.com>
Date: Mon, 27 Jan 2025 20:07:55 +0100
From: "Arnd Bergmann" <arnd@...db.de>
To: "Xu Lu" <luxu.kernel@...edance.com>
Cc: "Thomas Gleixner" <tglx@...utronix.de>,
 "Anup Patel" <anup@...infault.org>, "Charlie Jenkins" <charlie@...osinc.com>,
 "Paul Walmsley" <paul.walmsley@...ive.com>,
 "Palmer Dabbelt" <palmer@...belt.com>, lihangjing@...edance.com,
 "Xie Yongji" <xieyongji@...edance.com>, linux-riscv@...ts.infradead.org,
 linux-kernel@...r.kernel.org
Subject: Re: [External] Re: [PATCH RESEND] irqchip: riscv: Order normal writes and IPI
 writes

On Mon, Jan 27, 2025, at 17:37, Xu Lu wrote:
> On Tue, Jan 28, 2025 at 12:23 AM Arnd Bergmann <arnd@...db.de> wrote:
>> On Mon, Jan 27, 2025, at 10:38, Xu Lu wrote:
>>
>> thead_aclint_sswi_ipi_clear() seems to have the same bug,
>> it also uses the _relaxed() version for no apparent reason.
>
>
> There seems no need to modify thead_aclint_sswi_ipi_clear() as it only
> clears pending IPI on current hart. No other harts require to see
> strict order between preceding memory writes and this ACLINT MMIO
> write. Please correct me if I missed anything.

My point was that you should always default to the normal operations,
since the relaxed ones keep causing problems. If you still think it's
important to use writel_relaxed() in thead_aclint_sswi_ipi_clear(),
please add a comment explaining how you have shown that it's correct
and why it matters, otherwise convert them both.

      Arnd

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