linux-kernel - Re: [PATCH RFC net-next 1/2] net: pcs: xpcs: Add special code to operate in Microchip KSZ9477 switch

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Message-ID: <Z5jeJ_p22fF1AqDZ@shell.armlinux.org.uk>
Date: Tue, 28 Jan 2025 13:39:51 +0000
From: "Russell King (Oracle)" <linux@...linux.org.uk>
To: Andrew Lunn <andrew@...n.ch>
Cc: Tristram.Ha@...rochip.com, Woojung Huh <woojung.huh@...rochip.com>,
	Vladimir Oltean <olteanv@...il.com>,
	Heiner Kallweit <hkallweit1@...il.com>,
	Maxime Chevallier <maxime.chevallier@...tlin.com>,
	"David S. Miller" <davem@...emloft.net>,
	Eric Dumazet <edumazet@...gle.com>,
	Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
	UNGLinuxDriver@...rochip.com, netdev@...r.kernel.org,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH RFC net-next 1/2] net: pcs: xpcs: Add special code to
 operate in Microchip KSZ9477 switch

On Tue, Jan 28, 2025 at 02:16:28PM +0100, Andrew Lunn wrote:
> > For 1000BaseX mode setting neg_mode to false works, but that does not
> > work for SGMII mode.  Setting 0x18 value in register 0x1f8001 allows
> > 1000BaseX mode to work with auto-negotiation enabled.
> 
> Unless you have the datasheet, writing 0x18 to 0x1f8001 is pretty
> meaningless. You need to explain what these two bits mean in this
> register.

Well, this is the reason I searched for the datasheet to find out
what it was, and discovered further information which suggests
other stuff is wrong in the current driver.

bit 4: SGMII link status. This is used to populate the SGMII tx_config
register bit 15 when XPCS is operating in PHY mode. KSZ9477
documentation states that this bit must be set in "SerDes" mode, aka
1000base-X. If that requirement comes from Synopsys, then the current
XPCS driver is buggy...

bit 3: Transmit configuration. In SGMII mode, selects between PHY mode
(=1) or MAC mode (=0). KSZ9477 documentation states that this bit must
be set when operating in "SerDes" mode. (Same concern as for bit 4.)

I will also note here that bits 2:1 are documented as 00=SerDes mode,
10=SGMII mode.

Cross-referencing with the SJA1105 documentation, Digital Control
Register 1 bit 0 = 0 gives a tx_config format of:

	tx_config[15] = comes from SGMII link status above
	tx_config[12] = MII_ADVERTISE.bit5 (which, even though operating
			in SGMII mode, MII_ADVERTISE is 802.3z format.)
	tx_config[11:10] = MII_BMCR speed bits

As stated elsewhere, changes to the AN control register in KSZ9477
are documented as only taking effect when the MII_ADVERTISE register
is subsequently written (which the driver doesn't do, nor does this
patch!)

The lack of access to Synopsys Designware XPCS documentation makes
working out how to properly drive this hardware problematical. We're
subject to the randomness of the register set documentation that can
be found in various chip manufacturers who publish it.

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
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