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Message-ID: <28cb7ba0-877f-40fe-ae67-55a35446ba86@kernel.org>
Date: Wed, 29 Jan 2025 08:53:58 +0100
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Conor Dooley <conor@...nel.org>
Cc: patrice.chotard@...s.st.com, Mark Brown <broonie@...nel.org>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Alexandre Torgue <alexandre.torgue@...s.st.com>,
Philipp Zabel <p.zabel@...gutronix.de>,
Maxime Coquelin <mcoquelin.stm32@...il.com>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Arnd Bergmann <arnd@...db.de>, Catalin Marinas <catalin.marinas@....com>,
Will Deacon <will@...nel.org>, linux-spi@...r.kernel.org,
devicetree@...r.kernel.org, linux-stm32@...md-mailman.stormreply.com,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
christophe.kerello@...s.st.com
Subject: Re: [PATCH v2 1/9] dt-bindings: spi: Add STM32 OSPI controller
On 29/01/2025 08:40, Krzysztof Kozlowski wrote:
> On Tue, Jan 28, 2025 at 06:02:27PM +0000, Conor Dooley wrote:
>>> + st,syscfg-dlyb:
>>> + description: phandle to syscon block
>>> + Use to set the OSPI delay block within syscon to
>>> + tune the phase of the RX sampling clock (or DQS) in order
>>> + to sample the data in their valid window and to
>>> + tune the phase of the TX launch clock in order to meet setup
>>> + and hold constraints of TX signals versus the memory clock.
>>> + $ref: /schemas/types.yaml#/definitions/phandle-array
>>
>> Why do you need a phandle here? I assume looking up by compatible ain't
>> possible because you have multiple controllers on the SoC? Also, I don't
>> think your copy-paste "phandle to" stuff here is accurate:
>> st,syscfg-dlyb = <&syscfg 0x1000>;
>> There's an offset here that you don't mention in your description.
>
> This needs double items: and listing them with description, instead of
> free form text.
And I asked for this last time and I told you how to find examples doing
this. In other binding patch you did not implement all the comments either.
Best regards,
Krzysztof
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