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Message-ID: <20250129145155.1746876-3-andriy.shevchenko@linux.intel.com>
Date: Wed, 29 Jan 2025 16:49:40 +0200
From: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
To: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>,
	Hans de Goede <hdegoede@...hat.com>,
	linux-gpio@...r.kernel.org,
	linux-kernel@...r.kernel.org
Cc: Mika Westerberg <mika.westerberg@...ux.intel.com>,
	Andy Shevchenko <andy@...nel.org>,
	Linus Walleij <linus.walleij@...aro.org>
Subject: [PATCH v1 2/2] pinctrl: lynxpoint: Use dedicated helpers for chained IRQ handlers

Instead of relying on the fact that the parent IRQ chip supports
fasteoi mode and calling the respective callback at the end of
the interrupt handler, surround it with enter and exit helpers
for chained IRQ handlers which will consider all possible cases.

This in particular unifies how GPIO drivers handle IRQ.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
---
 drivers/pinctrl/intel/pinctrl-lynxpoint.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/pinctrl/intel/pinctrl-lynxpoint.c b/drivers/pinctrl/intel/pinctrl-lynxpoint.c
index cc5ede17c383..ac5459a4c63e 100644
--- a/drivers/pinctrl/intel/pinctrl-lynxpoint.c
+++ b/drivers/pinctrl/intel/pinctrl-lynxpoint.c
@@ -549,6 +549,8 @@ static void lp_gpio_irq_handler(struct irq_desc *desc)
 	unsigned long pending;
 	u32 base, pin;
 
+	chained_irq_enter(chip, desc);
+
 	/* check from GPIO controller which pin triggered the interrupt */
 	for (base = 0; base < lg->chip.ngpio; base += 32) {
 		reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT);
@@ -560,7 +562,8 @@ static void lp_gpio_irq_handler(struct irq_desc *desc)
 		for_each_set_bit(pin, &pending, 32)
 			generic_handle_domain_irq(lg->chip.irq.domain, base + pin);
 	}
-	chip->irq_eoi(data);
+
+	chained_irq_exit(chip, desc);
 }
 
 static void lp_irq_ack(struct irq_data *d)
-- 
2.43.0.rc1.1336.g36b5255a03ac


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