Message-ID: <d28f5482-81bc-4600-9a60-872dadd22b96@quicinc.com>
Date: Thu, 30 Jan 2025 11:10:45 +0530
From: Pratyush Brahma <quic_pbrahma@...cinc.com>
To: Konrad Dybcio <konrad.dybcio@....qualcomm.com>, <andersson@...nel.org>
CC: <konradybcio@...nel.org>, <robh@...nel.org>, <krzk+dt@...nel.org>,
        <conor+dt@...nel.org>, <linux-arm-msm@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        Prakash Gupta
	<quic_guptap@...cinc.com>
Subject: Re: [PATCH v3 2/2] arm64: dts: qcom: qcs8300: Add device node for
 gfx_smmu


On 1/29/2025 7:56 PM, Konrad Dybcio wrote:
> On 28.01.2025 11:02 AM, Pratyush Brahma wrote:
>> On 1/9/2025 8:56 PM, Konrad Dybcio wrote:
>>> On 8.01.2025 1:10 PM, Pratyush Brahma wrote:
>>>> On 12/30/2024 6:49 PM, Konrad Dybcio wrote:
>>>>> On 27.12.2024 12:00 PM, Pratyush Brahma wrote:
>>>>>> Add the device node for gfx smmu that is required for gpu
>>>>>> specific address translations.
>>>>>>
>>>>>> This patch depends on the patch series [1] posted by Imran Shaik
>>>>>> adding the clock support for gpu.
>>>>>>
>>>>>> [1] https://lore.kernel.org/all/802d32f1-ff7e-4d61-83f1-f804ee1750ed@oss.qualcomm.com/
>>>>>>
>>>>>> Signed-off-by: Pratyush Brahma <quic_pbrahma@...cinc.com>
>>>>>> ---
>>>>>>     arch/arm64/boot/dts/qcom/qcs8300.dtsi | 37 +++++++++++++++++++++++++++
>>>>>>     1 file changed, 37 insertions(+)
>>>>>>
>>>>>> diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>>>>>> index 80226992a65d..8eb688e2df0a 100644
>>>>>> --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>>>>>> +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>>>>>> @@ -816,6 +816,43 @@
>>>>>>                 #power-domain-cells = <1>;
>>>>>>             };
>>>>>>     +        adreno_smmu: iommu@...0000 {
>>>>>> +            compatible = "qcom,qcs8300-smmu-500", "qcom,adreno-smmu",
>>>>>> +                   "qcom,smmu-500", "arm,mmu-500";
>>>>>> +            reg = <0x0 0x3da0000 0x0 0x20000>;
>>>>>> +            #iommu-cells = <2>;
>>>>>> +            #global-interrupts = <2>;
>>>>>> +            dma-coherent;
>>>>>> +
>>>>>> +            power-domains = <&gpucc GPU_CC_CX_GDSC>;
>>>>>> +            clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
>>>>>> +                 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
>>>>>> +                 <&gpucc GPU_CC_AHB_CLK>,
>>>>>> +                 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
>>>>>> +                 <&gpucc GPU_CC_CX_GMU_CLK>,
>>>>>> +                 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
>>>>>> +                 <&gpucc GPU_CC_HUB_AON_CLK>;
>>>>>> +            clock-names = "gcc_gpu_memnoc_gfx_clk",
>>>>>> +                      "gcc_gpu_snoc_dvm_gfx_clk",
>>>>>> +                      "gpu_cc_ahb_clk",
>>>>>> +                      "gpu_cc_hlos1_vote_gpu_smmu_clk",
>>>>>> +                      "gpu_cc_cx_gmu_clk",
>>>>>> +                      "gpu_cc_hub_cx_int_clk",
>>>>>> +                      "gpu_cc_hub_aon_clk";
>>>>> Most of these entries look totally bogus, please make sure you only
>>>>> reference the ones actually required
>>>> These entries are exactly similar to the ones we use in sa8775p as well [1] and the usecases
>>>> haven't changed between qcs8300 and sa8775p.
>>>>
>>>> Can you please let me know which entries you find irrelevant here?
>>> Well, I'm particularly unsure about CX_GMU and the HUB clocks.
>>> I >>don't think<< they don't have much to do with the SMMU, but please
>>> check internally with someone who knows for sure
>> I checked internally and found that these clocks are required for gpu smmu operations
>> as we don't use interconnect voting mechanism here as we do downstream. Hence the
>> list of clocks is same across all targets using gpu smmu as described in [1] previously.
> I managed to dig up some documents too.. It seems you're right, however the order
> is supposed to be slightly different:
>
> GPU_CC_CX_GMU_CLK
> GPU_CC_HUB_CX_INT_CLK
> GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK
> GCC_GPU_MEMNOC_GFX_CLK
>
> Unsure if it *actually* matters given we've added them in a random order on a
> multitude of platforms and there haven't been any visible adverse effects.
Thanks for checking this. We haven't really adhered to this order in
most of our platforms and things have been running fine. So I guess it 
doesn't matter.
However, I'll still send out the next patchset in the order you've 
mentioned. Just so that we
are in consonance, the final order would look like the following. Please 
correct me if you'd
prefer otherwise.

                 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
                                <&gpucc GPU_CC_HUB_CX_INT_CLK>,
                                <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
                                <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
                                <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
                                <&gpucc GPU_CC_AHB_CLK>,
                                <&gpucc GPU_CC_HUB_AON_CLK>;

>
> With GPU_CC_AHB not being mentioned but it being quite reasonable to be there
> judging by its name. Enabling HLOS1_VOTE normally enables some more clocks (some
> known by Linux, some not), but here the docs are rather cryptic on that topic.
>
> I'm not sure about SNoC_DVM on this one as well, but other SoCs require it so
> it's probably safe so assume this one does so as well
Yes, I have been conservative to include all the clocks that are 
required on other platforms
here as well.
>
> I've verified the interrupt numbers, so please just alter the property order /
> whitespaces / general style of the node to match x1e80100.dtsi and we'll get
> this merged

Sure, will take care of this in the next version.

> Konrad

-- 
Thanks and Regards
Pratyush Brahma

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